clk: clk-vf610: Add clock for Vybrid OCOTP controller
authorSanchayan Maity <maitysanchayan@gmail.com>
Mon, 7 Sep 2015 08:21:35 +0000 (13:51 +0530)
committerShawn Guo <shawnguo@kernel.org>
Wed, 23 Sep 2015 01:02:40 +0000 (18:02 -0700)
Add clock support for Vybrid On-Chip One Time Programmable
(OCOTP) controller.

While the OCOTP block does not require explicit clock gating,
for programming the OCOTP timing register the clock rate of
ipg clock is required for timing calculations related to fuse
and shadow register read sequence. We explicitly specify the
ipg clock for OCOTP as a result.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-vf610.c
include/dt-bindings/clock/vf610-clock.h

index bff45ead7389976ecac2da81765e44d0753028cf..d1b1c95177bbeb577c88bf06c06121db76477f24 100644 (file)
@@ -387,6 +387,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 
        clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));
        clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24);
+       clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5));
 
        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
index d19763439472237589e216dd64d3b10863682259..56c16aaea112c776543f1548936c55e6db49cb2b 100644 (file)
 #define VF610_PLL7_BYPASS              181
 #define VF610_CLK_SNVS                 182
 #define VF610_CLK_DAP                  183
-#define VF610_CLK_END                  184
+#define VF610_CLK_OCOTP         184
+#define VF610_CLK_END                  185
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
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