drm/radeon/cayman: setup hdp to invalidate and flush when asked
authorDave Airlie <airlied@redhat.com>
Thu, 19 May 2011 04:14:42 +0000 (14:14 +1000)
committerDave Airlie <airlied@gmail.com>
Sun, 22 May 2011 10:25:27 +0000 (20:25 +1000)
On cayman we need to set the bit to cause HDP flushes to invalidate the
HDP cache also.

Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
cc: stable@kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/nid.h

index 7aade20f63a8c5fb932776a084aceffe5366faff..57d3d6c208d857cd51697e3fa49b90f0f1a4166a 100644 (file)
@@ -931,6 +931,10 @@ static void cayman_gpu_init(struct radeon_device *rdev)
        WREG32(CB_PERF_CTR3_SEL_0, 0);
        WREG32(CB_PERF_CTR3_SEL_1, 0);
 
+       tmp = RREG32(HDP_MISC_CNTL);
+       tmp |= HDP_FLUSH_INVALIDATE_CACHE;
+       WREG32(HDP_MISC_CNTL, tmp);
+
        hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
        WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 
index 0f9a08b53fbd4b9b4e4e90e8c63aad02a554f229..b2088c1981d82872054b860b0acea8dc48683812 100644 (file)
 #define        HDP_NONSURFACE_INFO                             0x2C08
 #define        HDP_NONSURFACE_SIZE                             0x2C0C
 #define HDP_ADDR_CONFIG                                0x2F48
+#define HDP_MISC_CNTL                                  0x2F4C
+#define        HDP_FLUSH_INVALIDATE_CACHE                      (1 << 0)
 
 #define        CC_SYS_RB_BACKEND_DISABLE                       0x3F88
 #define        GC_USER_SYS_RB_BACKEND_DISABLE                  0x3F8C
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