ARM: dts: vf610: add system reset controller and syscon-reboot

Add the system reset controller (SRC) module and use syscon-reboot
to register a restart handler which restarts the SoC using the
SRC SW_RST bit.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index ea0f74f6eeb3a7a754d08cd5bdcaf5b8c53f6b9d..29016090d0601b00dd325eef8e29fcdecc0a8017 100644 (file)
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -130,6 +130,10 @@
        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&src {
+       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+};
+
 &uart0 {
        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 };

diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 712646814cc6af4fa3e6a3b735b074004d3eef51..a55e1f9a414d6afab524bcf74b8a5f1c0879c673 100644 (file)
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -43,6 +43,13 @@
                clock-frequency = <32768>;
        };
 
+       reboot: syscon-reboot {
+               compatible = "syscon-reboot";
+               regmap = <&src>;
+               offset = <0x0>;
+               mask = <0x1000>;
+       };
+
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -318,6 +325,11 @@
                                clocks = <&clks VF610_CLK_USBC0>;
                                status = "disabled";
                        };
+
+                       src: src@4006e000 {
+                               compatible = "fsl,vf610-src", "syscon";
+                               reg = <0x4006e000 0x1000>;
+                       };
                };
 
                aips1: aips-bus@40080000 {