sim: h8300 Fixed different behavior in preinc/predec.

* sim-main.h (h8_typecodes): Add operand type OP_REG_DEC, OP_REG_INC.
* compile.c (decode): Rewrite oprand type for specific case.
(fetch_1): Add handling OP_REG_DEC and OP_REG_INC.
(step_once): Fix operand fetch order.

diff --git a/sim/h8300/ChangeLog b/sim/h8300/ChangeLog
index b6d91c84be82c26675abfeae23281da0eb789aae..c07a592963b788cc3cff17fced5071c9c92c947e 100644 (file)
--- a/sim/h8300/ChangeLog
+++ b/sim/h8300/ChangeLog
@@ -1,3 +1,10 @@
+2021-05-28  Yoshinori Sato  <ysato@users.sourceforge.jp>
+
+       * sim-main.h (h8_typecodes): Add operand type OP_REG_DEC, OP_REG_INC.
+       * compile.c (decode): Rewrite oprand type for specific case.
+       (fetch_1): Add handling OP_REG_DEC and OP_REG_INC.
+       (step_once): Fix operand fetch order.
+
 2021-05-17  Mike Frysinger  <vapier@gentoo.org>
 
        * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.

diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index a45a676ad0e3dbe9556e4f97b510712aadc11bf1..01e9766790c8b6dd64068006c9d240d8bd0d9a80 100644 (file)
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -1100,6 +1100,35 @@ decode (SIM_DESC sd, int addr, unsigned char *data, decoded_inst *dst)
                      /* End of Processing for system calls.  */
                    }
 
+                 /* Use same register is specified for source
+                    and destination.
+                    The value of source will be the value after
+                    address calculation.  */
+                 if (OP_KIND (dst->opcode) != O_CMP &&
+                     OP_KIND (dst->src.type) == OP_REG &&
+                     (dst->src.reg & 7) == dst->dst.reg) {
+                   switch (OP_KIND (dst->dst.type))
+                     {
+                     case OP_POSTDEC:
+                       dst->src.type = X (OP_REG_DEC,
+                                          OP_SIZE (dst->dst.type));
+                       break;
+                     case OP_POSTINC:
+                       dst->src.type = X (OP_REG_INC,
+                                          OP_SIZE (dst->dst.type));
+                       break;
+                     case OP_PREINC:
+                       if (OP_KIND (dst->opcode) == O_MOV)
+                         dst->src.type = X (OP_REG_INC,
+                                            OP_SIZE (dst->dst.type));
+                       break;
+                     case OP_PREDEC:
+                       if (OP_KIND (dst->opcode) == O_MOV)
+                         dst->src.type = X (OP_REG_DEC,
+                                            OP_SIZE (dst->dst.type));
+                       break;
+                     }
+                 }
                  dst->next_pc = addr + len / 2;
                  return;
                }
@@ -1370,6 +1399,25 @@ fetch_1 (SIM_DESC sd, ea_type *arg, int *val, int twice)
       *val = abs;
       break;
 
+    case X (OP_REG_DEC, SB):   /* Register direct, affected decrement byte.  */
+      *val = GET_B_REG (rn) - 1;
+      break;
+    case X (OP_REG_DEC, SW):   /* Register direct, affected decrement word.  */
+      *val = GET_W_REG (rn) - 2;
+      break;
+    case X (OP_REG_DEC, SL):   /* Register direct, affected decrement long.  */
+      *val = GET_L_REG (rn) - 4;
+      break;
+    case X (OP_REG_INC, SB):   /* Register direct, affected increment byte.  */
+      *val = GET_B_REG (rn) + 1;
+      break;
+    case X (OP_REG_INC, SW):   /* Register direct, affected increment word.  */
+      *val = GET_W_REG (rn) + 2;
+      break;
+    case X (OP_REG_INC, SL):   /* Register direct, affected increment long.  */
+      *val = GET_L_REG (rn) + 4;
+      break;
+
     case X (OP_MEM, SB):       /* Why isn't this implemented?  */
     default:
       sim_engine_halt (sd, cpu, NULL, NULL_CIA, sim_stopped, SIM_SIGSEGV);
@@ -1981,7 +2029,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
 
        case O (O_AND, SB):             /* and.b */
          /* Fetch rd and ea.  */
-         if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd)) 
+         if (fetch2 (sd, &code->dst, &rd) || fetch (sd, &code->src, &ea))
            goto end;
          res = rd & ea;
          goto log8;
@@ -2002,7 +2050,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
 
        case O (O_OR, SB):              /* or.b */
          /* Fetch rd and ea.  */
-         if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd)) 
+         if (fetch2 (sd, &code->dst, &rd) || fetch (sd, &code->src, &ea))
            goto end;
          res = rd | ea;
          goto log8;

diff --git a/sim/h8300/sim-main.h b/sim/h8300/sim-main.h
index a0aa9ef1929a1f5c1cf9d097db269ffcd136b396..f27ba6827381de580e6b413e735bbb2e1a17d4c4 100644 (file)
--- a/sim/h8300/sim-main.h
+++ b/sim/h8300/sim-main.h
@@ -82,7 +82,9 @@ enum h8_typecodes {
   /* FIXME: memory indirect?  */
   OP_INDEXB,           /* Byte index mode */
   OP_INDEXW,           /* Word index mode */
-  OP_INDEXL            /* Long index mode */
+  OP_INDEXL,           /* Long index mode */
+  OP_REG_DEC,          /* Register direct. affect address decrement. */
+  OP_REG_INC,          /* Register direct. affect address increment. */
 };
 
 #include "sim-basics.h"