ARM: sunxi: dt: add nodes for the mbus clock
authorEmilio López <emilio@elopez.com.ar>
Mon, 23 Dec 2013 03:32:44 +0000 (00:32 -0300)
committerEmilio López <emilio@elopez.com.ar>
Sat, 28 Dec 2013 20:28:24 +0000 (17:28 -0300)
mbus is the memory bus clock, and it is present on both sun5i and sun7i
machines. Its register layout is compatible with the mod0 one.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
arch/arm/boot/dts/sun5i-a10s.dtsi
arch/arm/boot/dts/sun5i-a13.dtsi
arch/arm/boot/dts/sun7i-a20.dtsi

index 6de7d702c3233f4c191f51481770886f0e2f606c..e053db932c0df3de117d7e475f7e4d5eda219b4f 100644 (file)
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
                };
+
+               mbus_clk: clk@01c2015c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c2015c 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "mbus";
+               };
        };
 
        soc@01c00000 {
index c46ac65988541eb03bb73fa0b26e86d58f5548f4..227be94f0b9bf59430f22c5a8beabeaea61168fc 100644 (file)
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
                };
+
+               mbus_clk: clk@01c2015c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c2015c 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "mbus";
+               };
        };
 
        soc@01c00000 {
index bc999539ab035fc8651f5fd286b8852ca67bd469..ee68196050507a2f578afe4e944bd820735c0f8a 100644 (file)
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi3";
                };
+
+               mbus_clk: clk@01c2015c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c2015c 0x4>;
+                       clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
+                       clock-output-names = "mbus";
+               };
        };
 
        soc@01c00000 {
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