mmc: omap_hsmmc: fix timeout for cmd and data soft reset

With HSMMC_HAS_UPDATED_RESET reset of cmd/data (SRC/SRD) can be to
quick and can be missed resulting in wait for software timeout.
With cpu_relax timeout can be long and unpredictable. Use udelay
instead for timeout implementation.

Reported-by: Yuzheng Ma <mayuzheng@kedacom.com>
Tested-by: Yuzheng Ma <mayuzheng@kedacom.com>
Reviewed-by: Hein Tibosch <hein_tibosch@yahoo.es>
Signed-off-by: Jianpeng Ma <majianpeng@gmail.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Chris Ball <cjb@laptop.org>

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 53b53b5816878f3b78383829471a31cb05a6650b..4d1170fa34c04b9136c86306c002dcb3079a1739 100644 (file)
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -119,7 +119,8 @@
                BRR_EN | BWR_EN | TC_EN | CC_EN)
 
 #define MMC_AUTOSUSPEND_DELAY  100
-#define MMC_TIMEOUT_MS         20
+#define MMC_TIMEOUT_MS         20              /* 20 mSec */
+#define MMC_TIMEOUT_US         20000           /* 20000 micro Sec */
 #define OMAP_MMC_MIN_CLOCK     400000
 #define OMAP_MMC_MAX_CLOCK     52000000
 #define DRIVER_NAME            "omap_hsmmc"
@@ -967,8 +968,7 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
                                                   unsigned long bit)
 {
        unsigned long i = 0;
-       unsigned long limit = (loops_per_jiffy *
-                               msecs_to_jiffies(MMC_TIMEOUT_MS));
+       unsigned long limit = MMC_TIMEOUT_US;
 
        OMAP_HSMMC_WRITE(host->base, SYSCTL,
                         OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
@@ -980,13 +980,13 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
        if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
                while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
                                        && (i++ < limit))
-                       cpu_relax();
+                       udelay(1);
        }
        i = 0;
 
        while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
                (i++ < limit))
-               cpu_relax();
+               udelay(1);
 
        if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
                dev_err(mmc_dev(host->mmc),