ARM: dts: sun4i: Add A10 SRAM and SRAM controller
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Thu, 26 Mar 2015 14:53:44 +0000 (15:53 +0100)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 1 Jun 2015 09:13:26 +0000 (11:13 +0200)
The A10 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.

Add the SRAM controller, the SRAM that it drives and the section that can
be used by the various devices.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>
arch/arm/boot/dts/sun4i-a10-a1000.dts
arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
arch/arm/boot/dts/sun4i-a10-cubieboard.dts
arch/arm/boot/dts/sun4i-a10-hackberry.dts
arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
arch/arm/boot/dts/sun4i-a10-marsboard.dts
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
arch/arm/boot/dts/sun4i-a10-pcduino.dts
arch/arm/boot/dts/sun4i-a10.dtsi

index 8d220ba7f89920736fba8c079e0a057a1e5fd220..2630d78d9e0456b58039723151ca26128c6065d4 100644 (file)
        status = "okay";
 };
 
+&emac_sram {
+       status = "okay";
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_pins_a>;
index c7b0ba0cf416ed05ed70dee6c0a8fdb3c465ffec..93d435670ef1eeedb2b7d62dea8d730f16790dda 100644 (file)
        status = "okay";
 };
 
+&emac_sram {
+       status = "okay";
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_pins_a>;
index 170811088fae284b746214de9b9165df2c4aeac2..9afb4e0185935ee4ffdda47e3595cc352341364a 100644 (file)
        status = "okay";
 };
 
+&emac_sram {
+       status = "okay";
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_pins_a>;
index 6b944db678c87d5d3d32fe7967bb337f5336aa56..2b17c519915165cf821d3c86d5af4ee634eab1f9 100644 (file)
        status = "okay";
 };
 
+&emac_sram {
+       status = "okay";
+};
+
 &ir0 {
        pinctrl-names = "default";
        pinctrl-0 = <&ir0_rx_pins_a>;
index 483ddee1e38473f27aae5a4cc52b3fd8c6cfa999..dc2f2aeaff07895c999d354bcd294e376d785058 100644 (file)
        status = "okay";
 };
 
+&emac_sram {
+       status = "okay";
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_pins_a>;
index 0bc9501699433b54e64a1a3aa6ad135ed04c5c20..02158bcd64ee50c19cd45d845f666c52c496484d 100644 (file)
        status = "okay";
 };
 
+&emac_sram {
+       status = "okay";
+};
+
 &emac {
        pinctrl-names = "default";
        pinctrl-0 = <&emac_pins_a>;
index 31b95fccfba1f0ac4421e7d41cadf9d7382d8a8d..b64aa4eb071e34d49b384e1731657dce451aa972 100644 (file)
        status = "okay";
 };
 
+&emac_sram {
+       status = "okay";
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_pins_a>;
index 52c1777ff2396efc0609d9dd199e40261c55fdae..4e3e1b9d8217e356c9c11953ff84eb2eee4f48ad 100644 (file)
        status = "okay";
 };
 
+&emac_sram {
+       status = "okay";
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_pins_a>;
index d7f43e5caf49be10d3f76ba6de32d96adcdf09d6..61c03d1fe5303301a7ee44f1069c3865da958313 100644 (file)
                #size-cells = <1>;
                ranges;
 
+               sram-controller@01c00000 {
+                       compatible = "allwinner,sun4i-a10-sram-controller";
+                       reg = <0x01c00000 0x30>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       sram_a: sram@00000000 {
+                               compatible = "mmio-sram";
+                               reg = <0x00000000 0xc000>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0 0x00000000 0xc000>;
+
+                               emac_sram: sram-section@8000 {
+                                       compatible = "allwinner,sun4i-a10-sram-a3-a4";
+                                       reg = <0x8000 0x4000>;
+                                       status = "disabled";
+                               };
+                       };
+
+                       sram_d: sram@00010000 {
+                               compatible = "mmio-sram";
+                               reg = <0x00010000 0x1000>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0 0x00010000 0x1000>;
+
+                               otg_sram: sram-section@0000 {
+                                       compatible = "allwinner,sun4i-a10-sram-d";
+                                       reg = <0x0000 0x1000>;
+                                       status = "disabled";
+                               };
+                       };
+               };
+
                dma: dma-controller@01c02000 {
                        compatible = "allwinner,sun4i-a10-dma";
                        reg = <0x01c02000 0x1000>;
                        reg = <0x01c0b000 0x1000>;
                        interrupts = <55>;
                        clocks = <&ahb_gates 17>;
+                       allwinner,sram = <&emac_sram 1>;
                        status = "disabled";
                };
 
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