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drm/nv30-nv40: Fix postdivider mask when writing engine/memory PLLs.
author
Francisco Jerez
<currojerez@riseup.net>
Tue, 28 Sep 2010 01:22:15 +0000
(
03:22
+0200)
committer
Ben Skeggs
<bskeggs@redhat.com>
Mon, 4 Oct 2010 23:58:33 +0000
(09:58 +1000)
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nouveau_hw.c
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diff --git
a/drivers/gpu/drm/nouveau/nouveau_hw.c
b/drivers/gpu/drm/nouveau/nouveau_hw.c
index ebcf8a8190c29d947ff2f3f325b4895a0cd5464e..bed669a54a2da0692af9a9a1cd4a89064f4d0fd0 100644
(file)
--- a/
drivers/gpu/drm/nouveau/nouveau_hw.c
+++ b/
drivers/gpu/drm/nouveau/nouveau_hw.c
@@
-305,7
+305,7
@@
setPLL_double_lowregs(struct drm_device *dev, uint32_t NMNMreg,
bool mpll = Preg == 0x4020;
uint32_t oldPval = nvReadMC(dev, Preg);
uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
- uint32_t Pval = (oldPval & (mpll ? ~(0x
11 << 16) : ~(1
<< 16))) |
+ uint32_t Pval = (oldPval & (mpll ? ~(0x
77 << 16) : ~(7
<< 16))) |
0xc << 28 | pv->log2P << 16;
uint32_t saved4600 = 0;
/* some cards have different maskc040s */
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