This patch addresses the change in the June Armv8.1-M Mainline specification, that...

The instructions that this change apply to are:

  VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH

The updated documentation is here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf

Fixed this by removing the check for this warning from GAS as well as opcodes.

Added testcases to test that the warning is not generated for the instructions that have a 32-bit element size
and the same source and destination operand. Also fixed tests that would previously check for this warning.

gas	* config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE.
	* testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests.
	* testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests.
	* testsuite/gas/arm/mve-vqdmladh.d: New tests.
	* testsuite/gas/arm/mve-vqdmladh.s: New tests.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests.
	* testsuite/gas/arm/mve-vqdmlsdh.d: New tests.
	* testsuite/gas/arm/mve-vqdmlsdh.s: New tests.

opcodes	* arm-dis.c (is_mve_unpredictable): Stop marking some MVE
	instructions as UNPREDICTABLE.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 66f79ac68847ac8dc97529dc84a4427c61e9a52d..002fca39adf4fc76365b9a388c2ed508192a76e6 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
+
+       * config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE.
+       * testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests.
+       * testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests.
+       * testsuite/gas/arm/mve-vqdmladh.d: New tests.
+       * testsuite/gas/arm/mve-vqdmladh.s: New tests.
+       * testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests.
+       * testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests.
+       * testsuite/gas/arm/mve-vqdmlsdh.d: New tests.
+       * testsuite/gas/arm/mve-vqdmlsdh.s: New tests.
+
 2019-07-19  H.J. Lu  <hongjiu.lu@intel.com>
 
        * testsuite/gas/i386/noextreg.d: Pass -O0 to assembler.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index b70028f7c2e31c179196b3c9ea9665fbf4b0159f..aa082a60c73a3b0f71781e95763f47950d4314e9 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -17922,11 +17922,6 @@ do_mve_vqdmladh (void)
   else
     inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
 
-  if (et.size == 32
-      && (inst.operands[0].reg == inst.operands[1].reg
-         || inst.operands[0].reg == inst.operands[2].reg))
-    as_tsktsk (BAD_MVE_SRCDEST);
-
   mve_encode_qqq (0, et.size);
 }
 

diff --git a/gas/testsuite/gas/arm/mve-vqdmladh-bad.l b/gas/testsuite/gas/arm/mve-vqdmladh-bad.l
index 96057b8daf64b113188c4b1411372d71d4606f97..1f55d2684b6fb8d449d0d3a22618faa45dce6d7d 100644 (file)
--- a/gas/testsuite/gas/arm/mve-vqdmladh-bad.l
+++ b/gas/testsuite/gas/arm/mve-vqdmladh-bad.l
@@ -1,61 +1,53 @@
 [^:]*: Assembler messages:
 [^:]*:10: Error: bad type in SIMD instruction -- `vqdmladh.u32 q0,q1,q2'
 [^:]*:11: Error: bad type in SIMD instruction -- `vqdmladh.s64 q0,q1,q2'
-[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:14: Error: bad type in SIMD instruction -- `vqdmladhx.u32 q0,q1,q2'
-[^:]*:15: Error: bad type in SIMD instruction -- `vqdmladhx.s64 q0,q1,q2'
-[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmladh.u32 q0,q1,q2'
-[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmladh.s64 q0,q1,q2'
-[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmladhx.u32 q0,q1,q2'
-[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmladhx.s64 q0,q1,q2'
-[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
-[^:]*:32: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
-[^:]*:34: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
-[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladht.s32 q0,q1,q2'
-[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmladh.s32 q0,q1,q2'
-[^:]*:39: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
-[^:]*:40: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
-[^:]*:42: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
-[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladhxt.s32 q0,q1,q2'
-[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmladhx.s32 q0,q1,q2'
-[^:]*:47: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
-[^:]*:48: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
-[^:]*:50: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
-[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladht.s32 q0,q1,q2'
-[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmladh.s32 q0,q1,q2'
-[^:]*:55: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
-[^:]*:56: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
-[^:]*:58: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
-[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladhxt.s32 q0,q1,q2'
-[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmladhx.s32 q0,q1,q2'
+[^:]*:12: Error: bad type in SIMD instruction -- `vqdmladhx.u32 q0,q1,q2'
+[^:]*:13: Error: bad type in SIMD instruction -- `vqdmladhx.s64 q0,q1,q2'
+[^:]*:14: Error: bad type in SIMD instruction -- `vqrdmladh.u32 q0,q1,q2'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqrdmladh.s64 q0,q1,q2'
+[^:]*:16: Error: bad type in SIMD instruction -- `vqrdmladhx.u32 q0,q1,q2'
+[^:]*:17: Error: bad type in SIMD instruction -- `vqrdmladhx.s64 q0,q1,q2'
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
+[^:]*:24: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
+[^:]*:26: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
+[^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladht.s32 q0,q1,q2'
+[^:]*:29: Error: instruction missing MVE vector predication code -- `vqdmladh.s32 q0,q1,q2'
+[^:]*:31: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
+[^:]*:32: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
+[^:]*:34: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
+[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladhxt.s32 q0,q1,q2'
+[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmladhx.s32 q0,q1,q2'
+[^:]*:39: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
+[^:]*:40: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
+[^:]*:42: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
+[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladht.s32 q0,q1,q2'
+[^:]*:45: Error: instruction missing MVE vector predication code -- `vqrdmladh.s32 q0,q1,q2'
+[^:]*:47: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
+[^:]*:48: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
+[^:]*:50: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
+[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladhxt.s32 q0,q1,q2'
+[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmladhx.s32 q0,q1,q2'

diff --git a/gas/testsuite/gas/arm/mve-vqdmladh-bad.s b/gas/testsuite/gas/arm/mve-vqdmladh-bad.s
index 7cedb3934b7247e336695caddd792509099073fd..1466b8c7c5674486297e8a8a7d36c028d8b91ac4 100644 (file)
--- a/gas/testsuite/gas/arm/mve-vqdmladh-bad.s
+++ b/gas/testsuite/gas/arm/mve-vqdmladh-bad.s
@@ -9,20 +9,12 @@ it \cond
 .thumb
 vqdmladh.u32 q0, q1, q2
 vqdmladh.s64 q0, q1, q2
-vqdmladh.s32 q0, q0, q2
-vqdmladh.s32 q0, q1, q0
 vqdmladhx.u32 q0, q1, q2
 vqdmladhx.s64 q0, q1, q2
-vqdmladhx.s32 q0, q0, q2
-vqdmladhx.s32 q0, q1, q0
 vqrdmladh.u32 q0, q1, q2
 vqrdmladh.s64 q0, q1, q2
-vqrdmladh.s32 q0, q0, q2
-vqrdmladh.s32 q0, q1, q0
 vqrdmladhx.u32 q0, q1, q2
 vqrdmladhx.s64 q0, q1, q2
-vqrdmladhx.s32 q0, q0, q2
-vqrdmladhx.s32 q0, q1, q0
 cond vqdmladh
 cond vqdmladhx
 cond vqrdmladh

diff --git a/gas/testsuite/gas/arm/mve-vqdmladh.d b/gas/testsuite/gas/arm/mve-vqdmladh.d
index 5ea403684e7041db9f8109822fbc1b072739f4d2..3e4739f8da30b40ebd68dd752dfc6c5442d337df 100644 (file)
--- a/gas/testsuite/gas/arm/mve-vqdmladh.d
+++ b/gas/testsuite/gas/arm/mve-vqdmladh.d
@@ -1399,3 +1399,9 @@ Disassembly of section .text:
 [^>]*> ee22 0e05       vqrdmladhe.s32  q0, q1, q2
 [^>]*> ee12 1e05       vqrdmladhxt.s16 q0, q1, q2
 [^>]*> ee12 1e05       vqrdmladhxe.s16 q0, q1, q2
+[^>]*> ee20 0e00       vqdmladh.s32    q0, q0, q0
+[^>]*> ee20 0e01       vqrdmladh.s32   q0, q0, q0
+[^>]*> ee20 0e02       vqdmladh.s32    q0, q0, q1
+[^>]*> ee22 2e05       vqrdmladh.s32   q1, q1, q2
+[^>]*> ee26 4e04       vqdmladh.s32    q2, q3, q2
+[^>]*> ee28 6e07       vqrdmladh.s32   q3, q4, q3

diff --git a/gas/testsuite/gas/arm/mve-vqdmladh.s b/gas/testsuite/gas/arm/mve-vqdmladh.s
index 63ce225e3bd3c319020f30bca9698acea000ab21..67a5b8d36eaa8da5bfab455ddd103fdcfdd56d7c 100644 (file)
--- a/gas/testsuite/gas/arm/mve-vqdmladh.s
+++ b/gas/testsuite/gas/arm/mve-vqdmladh.s
@@ -73,3 +73,9 @@ vqrdmladht.s32 q0, q1, q2
 vqrdmladhe.s32 q0, q1, q2
 vqrdmladhxt.s16 q0, q1, q2
 vqrdmladhxe.s16 q0, q1, q2
+vqdmladh.s32 q0, q0, q0
+vqrdmladh.s32 q0, q0, q0
+vqdmladh.s32 q0, q0, q1
+vqrdmladh.s32 q1, q1, q2
+vqdmladh.s32 q2, q3, q2
+vqrdmladh.s32 q3, q4, q3

diff --git a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
index 465476ccc1377d71aea25e42154cb87c6ac9e863..88c116b3d408822e7a2deff4151ffce95fd837e6 100644 (file)
--- a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
@@ -1,61 +1,53 @@
 [^:]*: Assembler messages:
 [^:]*:10: Error: bad type in SIMD instruction -- `vqdmlsdh.u32 q0,q1,q2'
 [^:]*:11: Error: bad type in SIMD instruction -- `vqdmlsdh.s64 q0,q1,q2'
-[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:14: Error: bad type in SIMD instruction -- `vqdmlsdhx.u32 q0,q1,q2'
-[^:]*:15: Error: bad type in SIMD instruction -- `vqdmlsdhx.s64 q0,q1,q2'
-[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmlsdh.u32 q0,q1,q2'
-[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmlsdh.s64 q0,q1,q2'
-[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmlsdhx.u32 q0,q1,q2'
-[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmlsdhx.s64 q0,q1,q2'
-[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:31: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
-[^:]*:32: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
-[^:]*:34: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
-[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdht.s32 q0,q1,q2'
-[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmlsdh.s32 q0,q1,q2'
-[^:]*:39: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
-[^:]*:40: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
-[^:]*:42: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
-[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdhxt.s32 q0,q1,q2'
-[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmlsdhx.s32 q0,q1,q2'
-[^:]*:47: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
-[^:]*:48: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
-[^:]*:50: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
-[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdht.s32 q0,q1,q2'
-[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmlsdh.s32 q0,q1,q2'
-[^:]*:55: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
-[^:]*:56: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
-[^:]*:58: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
-[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdhxt.s32 q0,q1,q2'
-[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmlsdhx.s32 q0,q1,q2'
+[^:]*:12: Error: bad type in SIMD instruction -- `vqdmlsdhx.u32 q0,q1,q2'
+[^:]*:13: Error: bad type in SIMD instruction -- `vqdmlsdhx.s64 q0,q1,q2'
+[^:]*:14: Error: bad type in SIMD instruction -- `vqrdmlsdh.u32 q0,q1,q2'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqrdmlsdh.s64 q0,q1,q2'
+[^:]*:16: Error: bad type in SIMD instruction -- `vqrdmlsdhx.u32 q0,q1,q2'
+[^:]*:17: Error: bad type in SIMD instruction -- `vqrdmlsdhx.s64 q0,q1,q2'
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
+[^:]*:24: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
+[^:]*:26: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
+[^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdht.s32 q0,q1,q2'
+[^:]*:29: Error: instruction missing MVE vector predication code -- `vqdmlsdh.s32 q0,q1,q2'
+[^:]*:31: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:32: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:34: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdhxt.s32 q0,q1,q2'
+[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmlsdhx.s32 q0,q1,q2'
+[^:]*:39: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
+[^:]*:40: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
+[^:]*:42: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
+[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdht.s32 q0,q1,q2'
+[^:]*:45: Error: instruction missing MVE vector predication code -- `vqrdmlsdh.s32 q0,q1,q2'
+[^:]*:47: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:48: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:50: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdhxt.s32 q0,q1,q2'
+[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmlsdhx.s32 q0,q1,q2'

diff --git a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
index 4c047a9373aa4b2e6195f0de932117becefde092..e458e5540ce2c6eec86a728a844f6aafeaeba9dd 100644 (file)
--- a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
@@ -9,20 +9,12 @@ it \cond
 .thumb
 vqdmlsdh.u32 q0, q1, q2
 vqdmlsdh.s64 q0, q1, q2
-vqdmlsdh.s32 q0, q0, q2
-vqdmlsdh.s32 q0, q1, q0
 vqdmlsdhx.u32 q0, q1, q2
 vqdmlsdhx.s64 q0, q1, q2
-vqdmlsdhx.s32 q0, q0, q2
-vqdmlsdhx.s32 q0, q1, q0
 vqrdmlsdh.u32 q0, q1, q2
 vqrdmlsdh.s64 q0, q1, q2
-vqrdmlsdh.s32 q0, q0, q2
-vqrdmlsdh.s32 q0, q1, q0
 vqrdmlsdhx.u32 q0, q1, q2
 vqrdmlsdhx.s64 q0, q1, q2
-vqrdmlsdhx.s32 q0, q0, q2
-vqrdmlsdhx.s32 q0, q1, q0
 cond vqdmlsdh
 cond vqdmlsdhx
 cond vqrdmlsdh

diff --git a/gas/testsuite/gas/arm/mve-vqdmlsdh.d b/gas/testsuite/gas/arm/mve-vqdmlsdh.d
index 783c9ca9a3db3bb3956c96631f847674079607d3..6b464fb4b0758641b1c77a43d4f6736d9e8b6a12 100644 (file)
--- a/gas/testsuite/gas/arm/mve-vqdmlsdh.d
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh.d
@@ -1399,3 +1399,9 @@ Disassembly of section .text:
 [^>]*> fe22 0e05       vqrdmlsdhe.s32  q0, q1, q2
 [^>]*> fe12 1e05       vqrdmlsdhxt.s16 q0, q1, q2
 [^>]*> fe12 1e05       vqrdmlsdhxe.s16 q0, q1, q2
+[^>]*> fe20 0e00       vqdmlsdh.s32    q0, q0, q0
+[^>]*> fe20 0e01       vqrdmlsdh.s32   q0, q0, q0
+[^>]*> fe22 2e04       vqdmlsdh.s32    q1, q1, q2
+[^>]*> fe24 4e07       vqrdmlsdh.s32   q2, q2, q3
+[^>]*> fe28 6e06       vqdmlsdh.s32    q3, q4, q3
+[^>]*> fe2a 8e09       vqrdmlsdh.s32   q4, q5, q4

diff --git a/gas/testsuite/gas/arm/mve-vqdmlsdh.s b/gas/testsuite/gas/arm/mve-vqdmlsdh.s
index 67b342ba5721a8f5e9c97f1b391f3ff03ea03771..3ff6888a79533fbf84b792974ea71c56eb2167b8 100644 (file)
--- a/gas/testsuite/gas/arm/mve-vqdmlsdh.s
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh.s
@@ -71,3 +71,9 @@ vqrdmlsdht.s32 q0, q1, q2
 vqrdmlsdhe.s32 q0, q1, q2
 vqrdmlsdhxt.s16 q0, q1, q2
 vqrdmlsdhxe.s16 q0, q1, q2
+vqdmlsdh.s32 q0, q0, q0
+vqrdmlsdh.s32 q0, q0, q0
+vqdmlsdh.s32 q1, q1, q2
+vqrdmlsdh.s32 q2, q2, q3
+vqdmlsdh.s32 q3, q4, q3
+vqrdmlsdh.s32 q4, q5, q4

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index f3b1cc35a0f2d7259d6edfb5a5964b2d217a8701..d1e6f03756d363fe289e8b5614f087d83ee0bae0 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -6546,10 +6546,6 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
        return FALSE;
       }
 
-    case MVE_VQRDMLADH:
-    case MVE_VQDMLSDH:
-    case MVE_VQRDMLSDH:
-    case MVE_VQDMLADH:
     case MVE_VMULL_INT:
       {
        unsigned long Qd;