* mn10300-opc.c (mn10300_opcodes): Fix mask field for

        mov am,(imm32,sp).
Found during initial simulator work.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f7e9e0a224fd2fb0f2091476b67dc47dba0349d8..a311be621d5f7928bdbddde7f392137a4d1f6699 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+Tue Nov 26 13:24:17 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * mn10300-opc.c (mn10300_opcodes): Fix mask field for
+       mov am,(imm32,sp).
+
 Tue Nov 26 10:53:21 1996  Ian Lance Taylor  <ian@cygnus.com>
 
        Add support for mips16 (16 bit MIPS implementation):

diff --git a/opcodes/mn10300-opc.c b/opcodes/mn10300-opc.c
index 1f1fdb750c41d6f021b6ba648a1f5f0b23818c12..a370073880cf54a703e1d834d1d90d519b206f72 100644 (file)
--- a/opcodes/mn10300-opc.c
+++ b/opcodes/mn10300-opc.c
@@ -240,7 +240,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov",       0xfc300000,     0xfff00000,     FMT_D4, {AM1, MEM2(IMM32,AN0)}},
 { "mov",       0x4300,         0xf300,         FMT_S1, {AM1, MEM2(IMM8, SP)}},
 { "mov",       0xfa900000,     0xfff30000,     FMT_D2, {AM1, MEM2(IMM16, SP)}},
-{ "mov",       0xfc900000,     0xfc930000,     FMT_D4, {AM1, MEM2(IMM32, SP)}},
+{ "mov",       0xfc900000,     0xfff30000,     FMT_D4, {AM1, MEM2(IMM32, SP)}},
 { "mov",       0xf3c0,         0xffc0,         FMT_D0, {AM2, MEM2(DI, AN0)}},
 { "mov",       0xfa800000,     0xfff30000,     FMT_D2, {AM1, MEM(IMM16_MEM)}},
 { "mov",       0xfc800000,     0xfff30000,     FMT_D4, {AM1, MEM(IMM32_MEM)}},