staging: comedi: ni_mio_common: open code the M-Series regmap offsets

Remove the enum m_series_register_offsets values that are only used in
the lookup tables for the STC to M-Series register mapping and just open
code the values. Having the extra level of indirection does not add any
additional clarity and it gets rid of some of the CamelCase symbols.

Some of the registers are not currently used by the driver so the mappings
were not present in the original switch code. Add the missing register
mappings to the lookup tables.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c
index ecfd0976a7761f2201b2177459a792959f69f534..fe7a6a0d06b2745be4d03c9f0b901d7aee2298d9 100644 (file)
--- a/drivers/staging/comedi/drivers/ni_mio_common.c
+++ b/drivers/staging/comedi/drivers/ni_mio_common.c
@@ -314,14 +314,14 @@ struct mio_regmap {
 };
 
 static const struct mio_regmap m_series_stc_write_regmap[] = {
-       [Interrupt_A_Ack_Register]      = { M_Offset_Interrupt_A_Ack, 2 },
-       [Interrupt_B_Ack_Register]      = { M_Offset_Interrupt_B_Ack, 2 },
-       [AI_Command_2_Register]         = { M_Offset_AI_Command_2, 2 },
-       [AO_Command_2_Register]         = { M_Offset_AO_Command_2, 2 },
-       [G_Command_Register(0)]         = { M_Offset_G0_Command, 2 },
-       [G_Command_Register(1)]         = { M_Offset_G1_Command, 2 },
-       [AI_Command_1_Register]         = { M_Offset_AI_Command_1, 2 },
-       [AO_Command_1_Register]         = { M_Offset_AO_Command_1, 2 },
+       [Interrupt_A_Ack_Register]      = { 0x104, 2 },
+       [Interrupt_B_Ack_Register]      = { 0x106, 2 },
+       [AI_Command_2_Register]         = { 0x108, 2 },
+       [AO_Command_2_Register]         = { 0x10a, 2 },
+       [G_Command_Register(0)]         = { 0x10c, 2 },
+       [G_Command_Register(1)]         = { 0x10e, 2 },
+       [AI_Command_1_Register]         = { 0x110, 2 },
+       [AO_Command_1_Register]         = { 0x112, 2 },
        [DIO_Output_Register]           = { 0, 0 }, /* DOES NOT MAP CLEANLY */
                                        /*
                                         * DIO_Output_Register maps to:
@@ -329,51 +329,59 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
                                         * { M_Offset_SCXI_Serial_Data_Out, 1 }
                                         */
        [DIO_Control_Register]          = { 0, 0 }, /* DOES NOT MAP CLEANLY */
-       [AI_Mode_1_Register]            = { M_Offset_AI_Mode_1, 2 },
-       [AI_Mode_2_Register]            = { M_Offset_AI_Mode_2, 2 },
-       [AI_SI_Load_A_Registers]        = { M_Offset_AI_SI_Load_A, 4 },
-       [AI_SC_Load_A_Registers]        = { M_Offset_AI_SC_Load_A, 4 },
-       [AI_SI2_Load_A_Register]        = { M_Offset_AI_SI2_Load_A, 4 },
-       [AI_SI2_Load_B_Register]        = { M_Offset_AI_SI2_Load_B, 4 },
-       [G_Mode_Register(0)]            = { M_Offset_G0_Mode, 2 },
-       [G_Mode_Register(1)]            = { M_Offset_G1_Mode, 2 },
-       [G_Load_A_Register(0)]          = { M_Offset_G0_Load_A, 4 },
-       [G_Load_B_Register(0)]          = { M_Offset_G0_Load_B, 4 },
-       [G_Load_A_Register(1)]          = { M_Offset_G1_Load_A, 4 },
-       [G_Load_B_Register(1)]          = { M_Offset_G1_Load_B, 4 },
-       [G_Input_Select_Register(0)]    = { M_Offset_G0_Input_Select, 2 },
-       [G_Input_Select_Register(1)]    = { M_Offset_G1_Input_Select, 2 },
-       [AO_Mode_1_Register]            = { M_Offset_AO_Mode_1, 2 },
-       [AO_Mode_2_Register]            = { M_Offset_AO_Mode_2, 2 },
-       [AO_UI_Load_A_Register]         = { M_Offset_AO_UI_Load_A, 4 },
-       [AO_BC_Load_A_Register]         = { M_Offset_AO_BC_Load_A, 4 },
-       [AO_UC_Load_A_Register]         = { M_Offset_AO_UC_Load_A, 4 },
-       [Clock_and_FOUT_Register]       = { M_Offset_Clock_and_FOUT, 2 },
-       [IO_Bidirection_Pin_Register]   = { M_Offset_IO_Bidirection_Pin, 2 },
-       [RTSI_Trig_Direction_Register]  = { M_Offset_RTSI_Trig_Direction, 2 },
-       [Interrupt_Control_Register]    = { M_Offset_Interrupt_Control, 2 },
-       [AI_Output_Control_Register]    = { M_Offset_AI_Output_Control, 2 },
-       [Analog_Trigger_Etc_Register]   = { M_Offset_Analog_Trigger_Etc, 2 },
-       [AI_START_STOP_Select_Register] = { M_Offset_AI_START_STOP_Select, 2 },
-       [AI_Trigger_Select_Register]    = { M_Offset_AI_Trigger_Select, 2 },
-       [AO_Start_Select_Register]      = { M_Offset_AO_Start_Select, 2 },
-       [AO_Trigger_Select_Register]    = { M_Offset_AO_Trigger_Select, 2 },
-       [G_Autoincrement_Register(0)]   = { M_Offset_G0_Autoincrement, 2 },
-       [G_Autoincrement_Register(1)]   = { M_Offset_G1_Autoincrement, 2 },
-       [AO_Mode_3_Register]            = { M_Offset_AO_Mode_3, 2 },
-       [Joint_Reset_Register]          = { M_Offset_Joint_Reset, 2 },
-       [Interrupt_A_Enable_Register]   = { M_Offset_Interrupt_A_Enable, 2 },
-       [Interrupt_B_Enable_Register]   = { M_Offset_Interrupt_B_Enable, 2 },
-       [AI_Personal_Register]          = { M_Offset_AI_Personal, 2 },
-       [AO_Personal_Register]          = { M_Offset_AO_Personal, 2 },
-       [RTSI_Trig_A_Output_Register]   = { M_Offset_RTSI_Trig_A_Output, 2 },
-       [RTSI_Trig_B_Output_Register]   = { M_Offset_RTSI_Trig_B_Output, 2 },
-       [Configuration_Memory_Clear]    = { M_Offset_Configuration_Memory_Clear,
-                                           2 },
-       [ADC_FIFO_Clear]                = { M_Offset_AI_FIFO_Clear, 2 },
-       [DAC_FIFO_Clear]                = { M_Offset_AO_FIFO_Clear, 2 },
-       [AO_Output_Control_Register]    = { M_Offset_AO_Output_Control, 2 },
-       [AI_Mode_3_Register]            = { M_Offset_AI_Mode_3, 2 },
+       [AI_Mode_1_Register]            = { 0x118, 2 },
+       [AI_Mode_2_Register]            = { 0x11a, 2 },
+       [AI_SI_Load_A_Registers]        = { 0x11c, 4 },
+       [AI_SI_Load_B_Registers]        = { 0x120, 4 },
+       [AI_SC_Load_A_Registers]        = { 0x124, 4 },
+       [AI_SC_Load_B_Registers]        = { 0x128, 4 },
+       [AI_SI2_Load_A_Register]        = { 0x12c, 4 },
+       [AI_SI2_Load_B_Register]        = { 0x130, 4 },
+       [G_Mode_Register(0)]            = { 0x134, 2 },
+       [G_Mode_Register(1)]            = { 0x136, 2 },
+       [G_Load_A_Register(0)]          = { 0x138, 4 },
+       [G_Load_B_Register(0)]          = { 0x13c, 4 },
+       [G_Load_A_Register(1)]          = { 0x140, 4 },
+       [G_Load_B_Register(1)]          = { 0x144, 4 },
+       [G_Input_Select_Register(0)]    = { 0x148, 2 },
+       [G_Input_Select_Register(1)]    = { 0x14a, 2 },
+       [AO_Mode_1_Register]            = { 0x14c, 2 },
+       [AO_Mode_2_Register]            = { 0x14e, 2 },
+       [AO_UI_Load_A_Register]         = { 0x150, 4 },
+       [AO_UI_Load_B_Register]         = { 0x154, 4 },
+       [AO_BC_Load_A_Register]         = { 0x158, 4 },
+       [AO_BC_Load_B_Register]         = { 0x15c, 4 },
+       [AO_UC_Load_A_Register]         = { 0x160, 4 },
+       [AO_UC_Load_B_Register]         = { 0x164, 4 },
+       [Clock_and_FOUT_Register]       = { 0x170, 2 },
+       [IO_Bidirection_Pin_Register]   = { 0x172, 2 },
+       [RTSI_Trig_Direction_Register]  = { 0x174, 2 },
+       [Interrupt_Control_Register]    = { 0x176, 2 },
+       [AI_Output_Control_Register]    = { 0x178, 2 },
+       [Analog_Trigger_Etc_Register]   = { 0x17a, 2 },
+       [AI_START_STOP_Select_Register] = { 0x17c, 2 },
+       [AI_Trigger_Select_Register]    = { 0x17e, 2 },
+       [AI_DIV_Load_A_Register]        = { 0x180, 4 },
+       [AO_Start_Select_Register]      = { 0x184, 2 },
+       [AO_Trigger_Select_Register]    = { 0x186, 2 },
+       [G_Autoincrement_Register(0)]   = { 0x188, 2 },
+       [G_Autoincrement_Register(1)]   = { 0x18a, 2 },
+       [AO_Mode_3_Register]            = { 0x18c, 2 },
+       [Joint_Reset_Register]          = { 0x190, 2 },
+       [Interrupt_A_Enable_Register]   = { 0x192, 2 },
+       [Second_IRQ_A_Enable_Register]  = { 0, 0 }, /* E-Series only */
+       [Interrupt_B_Enable_Register]   = { 0x196, 2 },
+       [Second_IRQ_B_Enable_Register]  = { 0, 0 }, /* E-Series only */
+       [AI_Personal_Register]          = { 0x19a, 2 },
+       [AO_Personal_Register]          = { 0x19c, 2 },
+       [RTSI_Trig_A_Output_Register]   = { 0x19e, 2 },
+       [RTSI_Trig_B_Output_Register]   = { 0x1a0, 2 },
+       [RTSI_Board_Register]           = { 0, 0 }, /* Unknown */
+       [Configuration_Memory_Clear]    = { 0x1a4, 2 },
+       [ADC_FIFO_Clear]                = { 0x1a6, 2 },
+       [DAC_FIFO_Clear]                = { 0x1a8, 2 },
+       [AO_Output_Control_Register]    = { 0x1ac, 2 },
+       [AI_Mode_3_Register]            = { 0x1ae, 2 },
 };
 
 static void m_series_stc_write(struct comedi_device *dev,
@@ -404,17 +412,24 @@ static void m_series_stc_write(struct comedi_device *dev,
 }
 
 static const struct mio_regmap m_series_stc_read_regmap[] = {
-       [AI_Status_1_Register]          = { M_Offset_AI_Status_1, 2 },
-       [AO_Status_1_Register]          = { M_Offset_AO_Status_1, 2 },
-       [G_Status_Register]             = { M_Offset_G01_Status, 2 },
-       [AO_Status_2_Register]          = { M_Offset_AO_Status_2, 2 },
-       [G_HW_Save_Register(0)]         = { M_Offset_G0_HW_Save, 4 },
-       [G_HW_Save_Register(1)]         = { M_Offset_G1_HW_Save, 4 },
-       [G_Save_Register(0)]            = { M_Offset_G0_Save, 4 },
-       [G_Save_Register(1)]            = { M_Offset_G1_Save, 4 },
-       [Joint_Status_1_Register]       = { M_Offset_Joint_Status_1, 2 },
-       [DIO_Serial_Input_Register]     = { M_Offset_SCXI_Serial_Data_In, 1 },
-       [Joint_Status_2_Register]       = { M_Offset_Joint_Status_2, 2 },
+       [AI_Status_1_Register]          = { 0x104, 2 },
+       [AO_Status_1_Register]          = { 0x106, 2 },
+       [G_Status_Register]             = { 0x108, 2 },
+       [AI_Status_2_Register]          = { 0, 0 }, /* Unknown */
+       [AO_Status_2_Register]          = { 0x10c, 2 },
+       [DIO_Parallel_Input_Register]   = { 0, 0 }, /* Unknown */
+       [G_HW_Save_Register(0)]         = { 0x110, 4 },
+       [G_HW_Save_Register(1)]         = { 0x114, 4 },
+       [G_Save_Register(0)]            = { 0x118, 4 },
+       [G_Save_Register(1)]            = { 0x11c, 4 },
+       [AO_UI_Save_Registers]          = { 0x120, 4 },
+       [AO_BC_Save_Registers]          = { 0x124, 4 },
+       [AO_UC_Save_Registers]          = { 0x128, 4 },
+       [Joint_Status_1_Register]       = { 0x136, 2 },
+       [DIO_Serial_Input_Register]     = { 0x009, 1 },
+       [Joint_Status_2_Register]       = { 0x13a, 2 },
+       [AI_SI_Save_Registers]          = { 0x180, 4 },
+       [AI_SC_Save_Registers]          = { 0x184, 4 },
 };
 
 static unsigned int m_series_stc_read(struct comedi_device *dev,

diff --git a/drivers/staging/comedi/drivers/ni_stc.h b/drivers/staging/comedi/drivers/ni_stc.h
index bd69c3f0acdc826d91c646946950848d3782b298..9a1946e4d02addb190f0175373a235867c1f9819 100644 (file)
--- a/drivers/staging/comedi/drivers/ni_stc.h
+++ b/drivers/staging/comedi/drivers/ni_stc.h
@@ -924,7 +924,6 @@ enum m_series_register_offsets {
        M_Offset_CDIO_DMA_Select = 0x7, /*  write */
        M_Offset_SCXI_Status = 0x7,     /*  read */
        M_Offset_AI_AO_Select = 0x9,    /*  write, same offset as e-series */
-       M_Offset_SCXI_Serial_Data_In = 0x9,     /*  read */
        M_Offset_G0_G1_Select = 0xb,    /*  write, same offset as e-series */
        M_Offset_Misc_Command = 0xf,
        M_Offset_SCXI_Serial_Data_Out = 0x11,
@@ -947,88 +946,7 @@ enum m_series_register_offsets {
        M_Offset_PFI_Filter = 0xb0,
        M_Offset_RTSI_Filter = 0xb4,
        M_Offset_SCXI_Legacy_Compatibility = 0xbc,
-       M_Offset_Interrupt_A_Ack = 0x104,       /*  write */
-       M_Offset_AI_Status_1 = 0x104,   /*  read */
-       M_Offset_Interrupt_B_Ack = 0x106,       /*  write */
-       M_Offset_AO_Status_1 = 0x106,   /*  read */
-       M_Offset_AI_Command_2 = 0x108,  /*  write */
-       M_Offset_G01_Status = 0x108,    /*  read */
-       M_Offset_AO_Command_2 = 0x10a,
-       M_Offset_AO_Status_2 = 0x10c,   /*  read */
-       M_Offset_G0_Command = 0x10c,    /*  write */
-       M_Offset_G1_Command = 0x10e,    /*  write */
-       M_Offset_G0_HW_Save = 0x110,
-       M_Offset_G0_HW_Save_High = 0x110,
-       M_Offset_AI_Command_1 = 0x110,
-       M_Offset_G0_HW_Save_Low = 0x112,
-       M_Offset_AO_Command_1 = 0x112,
-       M_Offset_G1_HW_Save = 0x114,
-       M_Offset_G1_HW_Save_High = 0x114,
-       M_Offset_G1_HW_Save_Low = 0x116,
-       M_Offset_AI_Mode_1 = 0x118,
-       M_Offset_G0_Save = 0x118,
-       M_Offset_G0_Save_High = 0x118,
-       M_Offset_AI_Mode_2 = 0x11a,
-       M_Offset_G0_Save_Low = 0x11a,
-       M_Offset_AI_SI_Load_A = 0x11c,
-       M_Offset_G1_Save = 0x11c,
-       M_Offset_G1_Save_High = 0x11c,
-       M_Offset_G1_Save_Low = 0x11e,
-       M_Offset_AI_SI_Load_B = 0x120,  /*  write */
-       M_Offset_AO_UI_Save = 0x120,    /*  read */
-       M_Offset_AI_SC_Load_A = 0x124,  /*  write */
-       M_Offset_AO_BC_Save = 0x124,    /*  read */
-       M_Offset_AI_SC_Load_B = 0x128,  /*  write */
-       M_Offset_AO_UC_Save = 0x128,    /* read */
-       M_Offset_AI_SI2_Load_A = 0x12c,
-       M_Offset_AI_SI2_Load_B = 0x130,
-       M_Offset_G0_Mode = 0x134,
-       M_Offset_G1_Mode = 0x136,       /*  write */
-       M_Offset_Joint_Status_1 = 0x136,        /*  read */
-       M_Offset_G0_Load_A = 0x138,
-       M_Offset_Joint_Status_2 = 0x13a,
-       M_Offset_G0_Load_B = 0x13c,
-       M_Offset_G1_Load_A = 0x140,
-       M_Offset_G1_Load_B = 0x144,
-       M_Offset_G0_Input_Select = 0x148,
-       M_Offset_G1_Input_Select = 0x14a,
-       M_Offset_AO_Mode_1 = 0x14c,
-       M_Offset_AO_Mode_2 = 0x14e,
-       M_Offset_AO_UI_Load_A = 0x150,
-       M_Offset_AO_UI_Load_B = 0x154,
-       M_Offset_AO_BC_Load_A = 0x158,
-       M_Offset_AO_BC_Load_B = 0x15c,
-       M_Offset_AO_UC_Load_A = 0x160,
-       M_Offset_AO_UC_Load_B = 0x164,
-       M_Offset_Clock_and_FOUT = 0x170,
-       M_Offset_IO_Bidirection_Pin = 0x172,
-       M_Offset_RTSI_Trig_Direction = 0x174,
-       M_Offset_Interrupt_Control = 0x176,
-       M_Offset_AI_Output_Control = 0x178,
-       M_Offset_Analog_Trigger_Etc = 0x17a,
-       M_Offset_AI_START_STOP_Select = 0x17c,
-       M_Offset_AI_Trigger_Select = 0x17e,
-       M_Offset_AI_SI_Save = 0x180,    /*  read */
-       M_Offset_AI_DIV_Load_A = 0x180, /*  write */
-       M_Offset_AI_SC_Save = 0x184,    /*  read */
-       M_Offset_AO_Start_Select = 0x184,       /*  write */
-       M_Offset_AO_Trigger_Select = 0x186,
-       M_Offset_AO_Mode_3 = 0x18c,
-       M_Offset_G0_Autoincrement = 0x188,
-       M_Offset_G1_Autoincrement = 0x18a,
-       M_Offset_Joint_Reset = 0x190,
-       M_Offset_Interrupt_A_Enable = 0x192,
-       M_Offset_Interrupt_B_Enable = 0x196,
-       M_Offset_AI_Personal = 0x19a,
-       M_Offset_AO_Personal = 0x19c,
-       M_Offset_RTSI_Trig_A_Output = 0x19e,
-       M_Offset_RTSI_Trig_B_Output = 0x1a0,
        M_Offset_RTSI_Shared_MUX = 0x1a2,
-       M_Offset_AO_Output_Control = 0x1ac,
-       M_Offset_AI_Mode_3 = 0x1ae,
-       M_Offset_Configuration_Memory_Clear = 0x1a4,
-       M_Offset_AI_FIFO_Clear = 0x1a6,
-       M_Offset_AO_FIFO_Clear = 0x1a8,
        M_Offset_G0_Counting_Mode = 0x1b0,
        M_Offset_G1_Counting_Mode = 0x1b2,
        M_Offset_G0_Second_Gate = 0x1b4,