stmmac: remove the mmc code (v3)
authorGiuseppe CAVALLARO <peppe.cavallaro@st.com>
Thu, 1 Sep 2011 21:51:36 +0000 (21:51 +0000)
committerDavid S. Miller <davem@davemloft.net>
Thu, 15 Sep 2011 19:40:00 +0000 (15:40 -0400)
DWMAC Management Counters (MMC) are not fully support.
The minimal support added in the past allowed to
only disable counters (if present) and mask their
interrupts.
This patch prepares the driver to support the MMC
removing obsolete code.

Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/common.h
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

index 375ea193e139a4a1bd23ecf68937007402682745..290b97a1925445cd6912b8c37eb5b39dd737804a 100644 (file)
@@ -130,17 +130,6 @@ enum tx_dma_irq_status {
 #define MAC_ENABLE_TX          0x00000008      /* Transmitter Enable */
 #define MAC_RNABLE_RX          0x00000004      /* Receiver Enable */
 
-/* MAC Management Counters register */
-#define MMC_CONTROL            0x00000100      /* MMC Control */
-#define MMC_HIGH_INTR          0x00000104      /* MMC High Interrupt */
-#define MMC_LOW_INTR           0x00000108      /* MMC Low Interrupt */
-#define MMC_HIGH_INTR_MASK     0x0000010c      /* MMC High Interrupt Mask */
-#define MMC_LOW_INTR_MASK      0x00000110      /* MMC Low Interrupt Mask */
-
-#define MMC_CONTROL_MAX_FRM_MASK       0x0003ff8       /* Maximum Frame Size */
-#define MMC_CONTROL_MAX_FRM_SHIFT      3
-#define MMC_CONTROL_MAX_FRAME          0x7FF
-
 struct stmmac_desc_ops {
        /* DMA RX descriptor ring initialization */
        void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
index eea184ab6d6495efaa56a64d6ec359d56e7ca5bf..9ba9cae5a60ab35bcd5803382f129edbeee80dc9 100644 (file)
@@ -37,8 +37,6 @@ static void dwmac1000_core_init(void __iomem *ioaddr)
        value |= GMAC_CORE_INIT;
        writel(value, ioaddr + GMAC_CONTROL);
 
-       /* Freeze MMC counters */
-       writel(0x8, ioaddr + GMAC_MMC_CTRL);
        /* Mask GMAC interrupts */
        writel(0x207, ioaddr + GMAC_INT_MASK);
 
index 743a58017637b2cf6eaf05328cd6d8857b724a80..aacfc6eade50710e6d8fd9757656d517705bd5ab 100644 (file)
@@ -70,17 +70,6 @@ static void dwmac100_dump_mac_regs(void __iomem *ioaddr)
                readl(ioaddr + MAC_VLAN1));
        pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
                readl(ioaddr + MAC_VLAN2));
-       pr_info("\n\tMAC management counter registers\n");
-       pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
-               MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
-       pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
-               MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
-       pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
-               MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
-       pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
-               MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
-       pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
-               MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
 }
 
 static void dwmac100_irq_status(void __iomem *ioaddr)
index 68fb5b0593a09056dc581ae8913c5d7ac74f5c32..579f2673fd2e136efff2df883fd6cdafa6e17f7d 100644 (file)
@@ -827,10 +827,6 @@ static int stmmac_open(struct net_device *dev)
                pr_info("\tTX Checksum insertion supported\n");
        netdev_update_features(dev);
 
-       /* Initialise the MMC (if present) to disable all interrupts. */
-       writel(0xffffffff, priv->ioaddr + MMC_HIGH_INTR_MASK);
-       writel(0xffffffff, priv->ioaddr + MMC_LOW_INTR_MASK);
-
        /* Request the IRQ lines */
        ret = request_irq(dev->irq, stmmac_interrupt,
                         IRQF_SHARED, dev->name, dev);
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