serial: sh-sci: Move SCBRR calculation algo in to platform data.
authorPaul Mundt <lethal@linux-sh.org>
Wed, 24 Jun 2009 09:23:52 +0000 (18:23 +0900)
committerPaul Mundt <lethal@linux-sh.org>
Wed, 24 Jun 2009 09:23:52 +0000 (18:23 +0900)
This permits each port to select its own SCBRR calculation algorithm,
rather than having it all ifdef'ed in the header. There are presently
only 5 different variations that all parts fall under.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
27 files changed:
arch/sh/kernel/cpu/sh2/setup-sh7619.c
arch/sh/kernel/cpu/sh2a/setup-mxg.c
arch/sh/kernel/cpu/sh2a/setup-sh7201.c
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
arch/sh/kernel/cpu/sh2a/setup-sh7206.c
arch/sh/kernel/cpu/sh3/setup-sh7705.c
arch/sh/kernel/cpu/sh3/setup-sh770x.c
arch/sh/kernel/cpu/sh3/setup-sh7710.c
arch/sh/kernel/cpu/sh3/setup-sh7720.c
arch/sh/kernel/cpu/sh4/setup-sh4-202.c
arch/sh/kernel/cpu/sh4/setup-sh7750.c
arch/sh/kernel/cpu/sh4/setup-sh7760.c
arch/sh/kernel/cpu/sh4a/setup-sh7343.c
arch/sh/kernel/cpu/sh4a/setup-sh7366.c
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
arch/sh/kernel/cpu/sh4a/setup-shx3.c
arch/sh/kernel/cpu/sh5/setup-sh5.c
drivers/serial/sh-sci.c
drivers/serial/sh-sci.h
include/linux/serial_sci.h

index ace016b1703623ec26147d56dc6742d1da5c560f..86acede777b99676b49b70a43474b37bda5c2c78 100644 (file)
@@ -64,18 +64,21 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xf8400000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 88, 88, 88, 88 },
        }, {
                .mapbase        = 0xf8410000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 92, 92, 92, 92 },
        }, {
                .mapbase        = 0xf8420000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 96, 96, 96, 96 },
        }, {
index 7ec658ce14f8323e4064d4a22bee3c8da828e8f6..b2c3bcc01190f0e580adc43cd5a42a227920a05e 100644 (file)
@@ -212,6 +212,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xff804000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 220, 220, 220, 220 },
        }, {
index 2a2ac222f9c722b7b27f40ebb2b09ac127a40b6a..8d44917ce50b533fe2ab63a20263d2766be8533c 100644 (file)
@@ -182,48 +182,56 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xfffe8000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 180, 180, 180, 180 }
        }, {
                .mapbase        = 0xfffe8800,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 184, 184, 184, 184 }
        }, {
                .mapbase        = 0xfffe9000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 188, 188, 188, 188 }
        }, {
                .mapbase        = 0xfffe9800,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 192, 192, 192, 192 }
        }, {
                .mapbase        = 0xfffea000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 196, 196, 196, 196 }
        }, {
                .mapbase        = 0xfffea800,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 200, 200, 200, 200 }
        }, {
                .mapbase        = 0xfffeb000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 204, 204, 204, 204 }
        }, {
                .mapbase        = 0xfffeb800,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 208, 208, 208, 208 }
        }, {
index 2c9f3ababfd764d45275e296fedae108f0d026e3..a78d2a219f3bfdcea28426f07977716db2237e29 100644 (file)
@@ -178,24 +178,28 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xfffe8000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           =  { 192, 192, 192, 192 },
        }, {
                .mapbase        = 0xfffe8800,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           =  { 196, 196, 196, 196 },
        }, {
                .mapbase        = 0xfffe9000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           =  { 200, 200, 200, 200 },
        }, {
                .mapbase        = 0xfffe9800,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           =  { 204, 204, 204, 204 },
        }, {
index 5a47987f3902a7952c7ff8fbf938d4aa3a701db7..68b93ed44cc252239c32679f0bf2e249a249a4aa 100644 (file)
@@ -138,24 +138,28 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xfffe8000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 240, 240, 240, 240 },
        }, {
                .mapbase        = 0xfffe8800,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 244, 244, 244, 244 },
        }, {
                .mapbase        = 0xfffe9000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 248, 248, 248, 248 },
        }, {
                .mapbase        = 0xfffe9800,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 252, 252, 252, 252 },
        }, {
index 28de53b281f3d8f9cca7d5bdca903d7f4a2adf42..27d03d836056f8fbb57d03ae45cc2b6bdd7d63e5 100644 (file)
@@ -73,12 +73,14 @@ static struct plat_sci_port sci_platform_data[] = {
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_TIE | SCSCR_RIE  | SCSCR_TE |
                                  SCSCR_RE  | SCSCR_CKE1 | SCSCR_CKE0,
+               .scbrr_algo_id  = SCBRR_ALGO_4,
                .type           = PORT_SCIF,
                .irqs           = { 56, 56, 56 },
        }, {
                .mapbase        = 0xa4400000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
+               .scbrr_algo_id  = SCBRR_ALGO_4,
                .type           = PORT_SCIF,
                .irqs           = { 52, 52, 52 },
        }, {
index 50ac42836dc7445a2669977b83b583937d397099..83c9a5a39685f2af1a984cef0758cd7b466b4f76 100644 (file)
@@ -111,6 +111,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xfffffe80,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_TE | SCSCR_RE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCI,
                .irqs           = { 23, 23, 23, 0 },
        },
@@ -121,6 +122,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xa4000150,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_TE | SCSCR_RE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 56, 56, 56, 56 },
        },
@@ -131,6 +133,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xa4000140,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_TE | SCSCR_RE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_IRDA,
                .irqs           = { 52, 52, 52, 52 },
        },
index 007627ecb7c85bdb46d6676c9a83888c9275f681..9a60ffd34a9f5721ccbed550f2cecaa3034ca221 100644 (file)
@@ -102,6 +102,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
                                  SCSCR_CKE1 | SCSCR_CKE0,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 52, 52, 52, 52 },
        }, {
@@ -109,6 +110,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
                                  SCSCR_CKE1 | SCSCR_CKE0,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 56, 56, 56, 56 },
        }, {
index 1fc3d90891990636a3f672087173b1a8abe758cf..48d50a65db321e4dc041b40d09f5590ce56580d8 100644 (file)
@@ -53,12 +53,14 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xa4430000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE,
+               .scbrr_algo_id  = SCBRR_ALGO_4,
                .type           = PORT_SCIF,
                .irqs           = { 80, 80, 80, 80 },
        }, {
                .mapbase        = 0xa4438000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE,
+               .scbrr_algo_id  = SCBRR_ALGO_4,
                .type           = PORT_SCIF,
                .irqs           = { 81, 81, 81, 81 },
        }, {
index 9aa6fa3ca4e6ad0226ead72addb28f4f411a8610..ec2104b49ef75944b91ec3acd5ffa1d0623abcf6 100644 (file)
@@ -20,6 +20,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe80000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 40, 41, 43, 42 },
        }, {
index 2159c439dce9f8c0eb170e0b71e449f1e69cdd16..51a945e0d72c37edefeb53968cf6aafa05572826 100644 (file)
@@ -41,6 +41,7 @@ static struct plat_sci_port sci_platform_data = {
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCI,
        .scscr          = SCSCR_TE | SCSCR_RE,
+       .scbrr_algo_id  = SCBRR_ALGO_2,
        .irqs           = { 23, 23, 23, 0 },
 };
 
@@ -55,6 +56,7 @@ static struct plat_sci_port scif_platform_data = {
        .mapbase        = 0xffe80000,
        .flags          = UPF_BOOT_AUTOCONF,
        .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
+       .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
        .irqs           = { 40, 40, 40, 40 },
 };
index 74b5e994724d6e911d09e07464acec45bf594704..cee660fe1d900ff633e1ed04d252e299c8bbdd01 100644 (file)
@@ -131,24 +131,28 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xfe600000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 52, 53, 55, 54 },
        }, {
                .mapbase        = 0xfe610000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 72, 73, 75, 74 },
        }, {
                .mapbase        = 0xfe620000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 76, 77, 79, 78 },
        }, {
                .mapbase        = 0xfe480000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCI,
                .irqs           = { 80, 81, 82, 0 },
        }, {
index 09fb5814d92526cba2c87a91185a6935ff21c96c..fbae06b1c98dd3294fcac003b6d9fd8ff8a738e7 100644 (file)
@@ -270,6 +270,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe00000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 80, 80, 80, 80 },
                .clk            = "scif0",
@@ -277,6 +278,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe10000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 81, 81, 81, 81 },
                .clk            = "scif1",
@@ -284,6 +286,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe20000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 82, 82, 82, 82 },
                .clk            = "scif2",
@@ -291,6 +294,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe30000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 83, 83, 83, 83 },
                .clk            = "scif3",
index 307777cf04cc59119872f79bb9a0b78d3875eb4f..d4ee429032b1058078af5bed63ab339dbe49c5c1 100644 (file)
@@ -281,6 +281,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe00000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 80, 80, 80, 80 },
                .clk            = "scif0",
index ffc69bc95932be89f304b7d38aae2139585b8cc0..f7b0551bf104d2b3f11730b18bb361ff7f54e91c 100644 (file)
@@ -306,6 +306,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe00000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 80, 80, 80, 80 },
                .clk            = "scif0",
@@ -313,6 +314,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe10000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 81, 81, 81, 81 },
                .clk            = "scif1",
@@ -320,6 +322,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe20000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 82, 82, 82, 82 },
                .clk            = "scif2",
index 6ce331a8f1bd08a1b01fcf0081217f6eadfba8df..bb4837b9dcf4d93ec0d6395e99049c85b48b5dcd 100644 (file)
@@ -322,6 +322,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe00000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 80, 80, 80, 80 },
                .clk            = "scif0",
@@ -329,6 +330,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe10000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 81, 81, 81, 81 },
                .clk            = "scif1",
@@ -336,6 +338,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe20000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 82, 82, 82, 82 },
                .clk            = "scif2",
@@ -343,6 +346,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xa4e30000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_3,
                .type           = PORT_SCIFA,
                .irqs           = { 56, 56, 56, 56 },
                .clk            = "scif3",
@@ -350,6 +354,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xa4e40000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_3,
                .type           = PORT_SCIFA,
                .irqs           = { 88, 88, 88, 88 },
                .clk            = "scif4",
@@ -357,6 +362,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xa4e50000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_3,
                .type           = PORT_SCIFA,
                .irqs           = { 109, 109, 109, 109 },
                .clk            = "scif5",
index 4bf03c1ec8d63c2e1b10a6258157ffe98520d520..c934b78e5658b4d0b26584764e6917d5613a5995 100644 (file)
@@ -29,6 +29,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe00000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 80, 80, 80, 80 },
                .clk            = "scif0",
@@ -36,6 +37,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe10000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 81, 81, 81, 81 },
                .clk            = "scif1",
@@ -43,6 +45,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe20000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 82, 82, 82, 82 },
                .clk            = "scif2",
@@ -50,6 +53,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xa4e30000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_3,
                .type           = PORT_SCIFA,
                .irqs           = { 56, 56, 56, 56 },
                .clk            = "scif3",
@@ -57,6 +61,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xa4e40000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_3,
                .type           = PORT_SCIFA,
                .irqs           = { 88, 88, 88, 88 },
                .clk            = "scif4",
@@ -64,6 +69,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xa4e50000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_3,
                .type           = PORT_SCIFA,
                .irqs           = { 109, 109, 109, 109 },
                .clk            = "scif5",
index 76339c6da01e2aa8388551124e75a5c5e71a1add..ab02771ee888af21afb827d42a066121e842c526 100644 (file)
@@ -41,18 +41,21 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe00000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 40, 40, 40, 40 },
        }, {
                .mapbase        = 0xffe08000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 76, 76, 76, 76 },
        }, {
                .mapbase        = 0xffe10000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 104, 104, 104, 104 },
        }, {
index 07a41ff20504d9424b5a5cad19c5f32789623e3f..746f4fb9ccf011ab6bb5d56c4d27b7a220ffca36 100644 (file)
@@ -19,60 +19,70 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xff923000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 61, 61, 61, 61 },
        }, {
                .mapbase        = 0xff924000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 62, 62, 62, 62 },
        }, {
                .mapbase        = 0xff925000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 63, 63, 63, 63 },
        }, {
                .mapbase        = 0xff926000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 64, 64, 64, 64 },
        }, {
                .mapbase        = 0xff927000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 65, 65, 65, 65 },
        }, {
                .mapbase        = 0xff928000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 66, 66, 66, 66 },
        }, {
                .mapbase        = 0xff929000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 67, 67, 67, 67 },
        }, {
                .mapbase        = 0xff92a000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 68, 68, 68, 68 },
        }, {
                .mapbase        = 0xff92b000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 69, 69, 69, 69 },
        }, {
                .mapbase        = 0xff92c000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 70, 70, 70, 70 },
        }, {
index 2b355b67a33d76462a19b9ca3d95f04c06edbe11..bcd411eb9cb0af50745eba36b077c2460c3f0113 100644 (file)
@@ -221,12 +221,14 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffe00000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 40, 40, 40, 40 },
        }, {
                .mapbase        = 0xffe10000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 76, 76, 76, 76 },
        }, {
index acd4b1d1b81336871f5c4e57118b65833abe00c2..3ae2e207100947b0a2e1d0bd3023f7244ed66c46 100644 (file)
@@ -203,6 +203,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffea0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 40, 40, 40, 40 },
                .clk            = "scif_fck",
@@ -210,6 +211,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffeb0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 44, 44, 44, 44 },
                .clk            = "scif_fck",
@@ -217,6 +219,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffec0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 60, 60, 60, 60 },
                .clk            = "scif_fck",
@@ -224,6 +227,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffed0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 61, 61, 61, 61 },
                .clk            = "scif_fck",
@@ -231,6 +235,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffee0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 62, 62, 62, 62 },
                .clk            = "scif_fck",
@@ -238,6 +243,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffef0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 63, 63, 63, 63 },
                .clk            = "scif_fck",
index 347ce88de5709479351dafe74a0bdb92f8b75f5b..8b7ea4bd965d5bb5e61676fe1d31c1635f3e9914 100644 (file)
@@ -28,6 +28,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffea0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 40, 41, 43, 42 },
        },
@@ -38,30 +39,35 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffeb0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 44, 44, 44, 44 },
        }, {
                .mapbase        = 0xffec0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 50, 50, 50, 50 },
        }, {
                .mapbase        = 0xffed0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 51, 51, 51, 51 },
        }, {
                .mapbase        = 0xffee0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 52, 52, 52, 52 },
        }, {
                .mapbase        = 0xffef0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+               .scbrr_algo_id  = SCBRR_ALGO_1,
                .type           = PORT_SCIF,
                .irqs           = { 53, 53, 53, 53 },
        }, {
index eef94934f542f55e78298c0103123e031b353589..4a26cc304139d3281c5a7755948872a602e97d6f 100644 (file)
@@ -20,24 +20,28 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = 0xffc30000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 40, 41, 43, 42 },
        }, {
                .mapbase        = 0xffc40000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 44, 45, 47, 46 },
        }, {
                .mapbase        = 0xffc50000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 48, 49, 51, 50 },
        }, {
                .mapbase        = 0xffc60000,
                .flags          = UPF_BOOT_AUTOCONF,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 52, 53, 55, 54 },
        }, {
index 26fa10c560de989f829d0e8689c2b87a2c9c7b06..72aa86ec744661c63cb23cc9c4dd4fc2a098a1be 100644 (file)
@@ -21,6 +21,7 @@ static struct plat_sci_port sci_platform_data[] = {
                .mapbase        = PHYS_PERIPHERAL_BLOCK + 0x01030000,
                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+               .scbrr_algo_id  = SCBRR_ALGO_2,
                .type           = PORT_SCIF,
                .irqs           = { 39, 40, 42, 0 },
        }, {
index 3a13e58e9c5d593ef661fc6a1ba7c18525c236e7..386fb878680cf455f910ec86591d200a263cae86 100644 (file)
@@ -82,6 +82,9 @@ struct sci_port {
        /* SCSCR initialization */
        unsigned int            scscr;
 
+       /* SCBRR calculation algo */
+       unsigned int            scbrr_algo_id;
+
 #ifdef CONFIG_HAVE_CLK
        /* Interface clock */
        struct clk              *iclk;
@@ -928,6 +931,27 @@ static void sci_shutdown(struct uart_port *port)
                s->disable(port);
 }
 
+static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
+                                  unsigned long freq)
+{
+       switch (algo_id) {
+       case SCBRR_ALGO_1:
+               return ((freq + 16 * bps) / (16 * bps) - 1);
+       case SCBRR_ALGO_2:
+               return ((freq + 16 * bps) / (32 * bps) - 1);
+       case SCBRR_ALGO_3:
+               return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
+       case SCBRR_ALGO_4:
+               return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
+       case SCBRR_ALGO_5:
+               return (((freq * 1000 / 32) / bps) - 1);
+       }
+
+       /* Warn, but use a safe default */
+       WARN_ON(1);
+       return ((freq + 16 * bps) / (32 * bps) - 1);
+}
+
 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
                            struct ktermios *old)
 {
@@ -937,7 +961,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
 
        baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
        if (likely(baud))
-               t = SCBRR_VALUE(baud, port->uartclk);
+               t = sci_scbrr_calc(s->scbrr_algo_id, baud, port->uartclk);
 
        do {
                status = sci_in(port, SCxSR);
@@ -1108,7 +1132,6 @@ static void __devinit sci_init_single(struct platform_device *dev,
        sci_port->type          = sci_port->port.type = p->type;
 
        memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
-
 }
 
 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
index 4aa0ac8e67dd9fd49e75e89fd92a33b252d345ae..81104777a0a636bf20dcbb34b326b05b2dd3130e 100644 (file)
@@ -713,59 +713,3 @@ static inline int sci_rxd_in(struct uart_port *port)
        return 1;
 }
 #endif
-
-/*
- * Values for the BitRate Register (SCBRR)
- *
- * The values are actually divisors for a frequency which can
- * be internal to the SH3 (14.7456MHz) or derived from an external
- * clock source.  This driver assumes the internal clock is used;
- * to support using an external clock source, config options or
- * possibly command-line options would need to be added.
- *
- * Also, to support speeds below 2400 (why?) the lower 2 bits of
- * the SCSMR register would also need to be set to non-zero values.
- *
- * -- Greg Banks 27Feb2000
- *
- * Answer: The SCBRR register is only eight bits, and the value in
- * it gets larger with lower baud rates. At around 2400 (depending on
- * the peripherial module clock) you run out of bits. However the
- * lower two bits of SCSMR allow the module clock to be divided down,
- * scaling the value which is needed in SCBRR.
- *
- * -- Stuart Menefy - 23 May 2000
- *
- * I meant, why would anyone bother with bitrates below 2400.
- *
- * -- Greg Banks - 7Jul2000
- *
- * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
- * tape reader as a console!
- *
- * -- Mitch Davis - 15 Jul 2000
- */
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7785) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7786)
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
-      defined(CONFIG_CPU_SUBTYPE_SH7724)
-static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
-{
-       if (port->type == PORT_SCIF)
-               return (clk+16*bps)/(32*bps)-1;
-       else
-               return ((clk*2)+16*bps)/(16*bps)-1;
-}
-#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
-#elif defined(__H8300H__) || defined(__H8300S__)
-#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#else /* Generic SH */
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
-#endif
index f722a2275add41a3768164d494d5683f37fee941..ff856b5bd276c16c1bb85feab94745652f9db747 100644 (file)
@@ -7,6 +7,14 @@
  * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
  */
 
+enum {
+       SCBRR_ALGO_1,           /* ((clk + 16 * bps) / (16 * bps) - 1) */
+       SCBRR_ALGO_2,           /* ((clk + 16 * bps) / (32 * bps) - 1) */
+       SCBRR_ALGO_3,           /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
+       SCBRR_ALGO_4,           /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
+       SCBRR_ALGO_5,           /* (((clk * 1000 / 32) / bps) - 1) */
+};
+
 #define SCSCR_TIE      (1 << 7)
 #define SCSCR_RIE      (1 << 6)
 #define SCSCR_TE       (1 << 5)
@@ -36,6 +44,7 @@ struct plat_sci_port {
        upf_t           flags;                  /* UPF_* flags */
        char            *clk;                   /* clock string */
 
+       unsigned int    scbrr_algo_id;          /* SCBRR calculation algo */
        unsigned int    scscr;                  /* SCSCR initialization */
 };
 
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