* mips.igen (SWC1) : Correct the handling of ReverseEndian

	and BigEndianCPU.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 93d77ba482685376b690b544010d8fc3d231cc8d..ce005707b3f8266cbd8a896338481f3638b2db97 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
+
+       * mips.igen (SWC1) : Correct the handling of ReverseEndian 
+       and BigEndianCPU.
+
 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 
        * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 48c6216859664669b6b1e2c182be17188a74662c..10ed6b8c0420539109e465e5195a2d013df1f8cd 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -5213,14 +5213,14 @@
          {
            uword64 memval = 0;
            uword64 memval1 = 0;
-           uword64 mask = 0x7;
+           uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+           address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
+           address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
            unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
-           byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
+           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+           byte = ((vaddr & mask) ^ bigendiancpu);
            memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
-           {
-             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
-           }
+           StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
          }
       }
   }