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drm/radeon/kms: flush HDP cache on GART table updates.
author
Dave Airlie
<airlied@redhat.com>
Mon, 15 Feb 2010 05:54:45 +0000
(15:54 +1000)
committer
Dave Airlie
<airlied@redhat.com>
Mon, 15 Feb 2010 05:54:45 +0000
(15:54 +1000)
Suggested by Alex Deucher @ AMD
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/r600.c
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diff --git
a/drivers/gpu/drm/radeon/r600.c
b/drivers/gpu/drm/radeon/r600.c
index 4facbab2045660b0033ef8530a5d50a88b26d798..6434d6af7d52d210bf7e72f9304d98afeda3a86c 100644
(file)
--- a/
drivers/gpu/drm/radeon/r600.c
+++ b/
drivers/gpu/drm/radeon/r600.c
@@
-370,6
+370,9
@@
void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
unsigned i;
u32 tmp;
+ /* flush hdp cache so updates hit vram */
+ WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+
WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
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