Merge branch 'sunxi/dt' into next/dt
authorArnd Bergmann <arnd@arndb.de>
Thu, 27 Nov 2014 15:05:30 +0000 (16:05 +0100)
committerArnd Bergmann <arnd@arndb.de>
Thu, 27 Nov 2014 15:05:30 +0000 (16:05 +0100)
This avoids a boot regression

* sunxi/dt:
  Revert "ARM: dts: sunxi: unify APB1 clock"
  Revert "ARM: dts: sunxi: Use sun4i-a10-apb1-clk for sun6i/sun8i apb2 clocks."

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/arm/boot/dts/sun4i-a10.dtsi
arch/arm/boot/dts/sun5i-a10s.dtsi
arch/arm/boot/dts/sun5i-a13.dtsi
arch/arm/boot/dts/sun6i-a31.dtsi
arch/arm/boot/dts/sun7i-a20.dtsi
arch/arm/boot/dts/sun8i-a23.dtsi

index 5e2ec2dd83339ea39de474e57908709703bdd969..380f914b226d527e0052df449a7f2fc33cb0c16c 100644 (file)
                                "apb0_ir1", "apb0_keypad";
                };
 
-               apb1: clk@01c20058 {
+               apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                       clock-output-names = "apb1_mux";
+               };
+
+               apb1: apb1@01c20058 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
+                       reg = <0x01c20058 0x4>;
+                       clocks = <&apb1_mux>;
                        clock-output-names = "apb1";
                };
 
index d2a85144d2d9d3b8d8b1ad39cb20faa16fb47c50..531272c0e526aec013c22ec6a7d6a3a044f88467 100644 (file)
                                "apb0_ir", "apb0_keypad";
                };
 
-               apb1: clk@01c20058 {
+               apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                       clock-output-names = "apb1_mux";
+               };
+
+               apb1: apb1@01c20058 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
+                       reg = <0x01c20058 0x4>;
+                       clocks = <&apb1_mux>;
                        clock-output-names = "apb1";
                };
 
index c35217ea1f6473653b4d67ce953f3c761fa043a0..b131068f4f351ca92e7df07d63641cec143c5fc2 100644 (file)
                        clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
                };
 
-               apb1: clk@01c20058 {
+               apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                       clock-output-names = "apb1_mux";
+               };
+
+               apb1: apb1@01c20058 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
+                       reg = <0x01c20058 0x4>;
+                       clocks = <&apb1_mux>;
                        clock-output-names = "apb1";
                };
 
index f1519a8a2ac7518aeb19f2f811f1ed9cb924811c..529c738039766cd92e94d6d71b5d93fe909f68a6 100644 (file)
                                        "apb1_daudio1";
                };
 
-               apb2: clk@01c20058 {
+               apb2_mux: apb2_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
+                       clock-output-names = "apb2_mux";
+               };
+
+               apb2: apb2@01c20058 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun6i-a31-apb2-div-clk";
+                       reg = <0x01c20058 0x4>;
+                       clocks = <&apb2_mux>;
                        clock-output-names = "apb2";
                };
 
index 7e30e267c3175a8687005102a75d7f41b73339d2..d7135f5282bc7c2d217e44e6af97b20176eeba94 100644 (file)
                                "apb0_iis2", "apb0_keypad";
                };
 
-               apb1: clk@01c20058 {
+               apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                       clock-output-names = "apb1_mux";
+               };
+
+               apb1: apb1@01c20058 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-apb1-clk";
+                       reg = <0x01c20058 0x4>;
+                       clocks = <&apb1_mux>;
                        clock-output-names = "apb1";
                };
 
index 0746cd1024d7a73b32bcbf6002954a4859d77ee5..6086adbf9d749adf1fb2040fb76675e84292bab9 100644 (file)
                                        "apb1_daudio0", "apb1_daudio1";
                };
 
-               apb2clk@01c20058 {
+               apb2_mux: apb2_mux_clk@01c20058 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-clk";
+                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                       clock-output-names = "apb2_mux";
+               };
+
+               apb2: apb2_clk@01c20058 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun6i-a31-apb2-div-clk";
+                       reg = <0x01c20058 0x4>;
+                       clocks = <&apb2_mux>;
                        clock-output-names = "apb2";
                };
 
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