ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1

Add hwmod data for the eDMA blocks:
 - TPCC: Third-party channel controller
 - TPTC0: Third-party transfer controller 0
 - TPTC1: Third-party transfer controller 1

The TPCC's clock gating status follows the status of its clock and
power domain. This means that the hwmod code can not directly control
the TPCC enable/disable status.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[paul@pwsan.com: rephrased last two sentences of the patch description]
Signed-off-by: Paul Walmsley <paul@pwsan.com>

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 252b74633e31d4ea2e72c6ce06c1fdcd24e45e41..9442d89bd2292bea0c4660abca067a632a7a56dd 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -429,6 +429,67 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = {
        .dev_attr       = &dma_dev_attr,
 };
 
+/*
+ * 'tpcc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
+       .name           = "tpcc",
+};
+
+static struct omap_hwmod dra7xx_tpcc_hwmod = {
+       .name           = "tpcc",
+       .class          = &dra7xx_tpcc_hwmod_class,
+       .clkdm_name     = "l3main1_clkdm",
+       .main_clk       = "l3_iclk_div",
+       .prcm           = {
+               .omap4  = {
+                       .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
+                       .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
+               },
+       },
+};
+
+/*
+ * 'tptc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
+       .name           = "tptc",
+};
+
+/* tptc0 */
+static struct omap_hwmod dra7xx_tptc0_hwmod = {
+       .name           = "tptc0",
+       .class          = &dra7xx_tptc_hwmod_class,
+       .clkdm_name     = "l3main1_clkdm",
+       .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+       .main_clk       = "l3_iclk_div",
+       .prcm           = {
+               .omap4  = {
+                       .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
+                       .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
+                       .modulemode   = MODULEMODE_HWCTRL,
+               },
+       },
+};
+
+/* tptc1 */
+static struct omap_hwmod dra7xx_tptc1_hwmod = {
+       .name           = "tptc1",
+       .class          = &dra7xx_tptc_hwmod_class,
+       .clkdm_name     = "l3main1_clkdm",
+       .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+       .main_clk       = "l3_iclk_div",
+       .prcm           = {
+               .omap4  = {
+                       .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
+                       .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
+                       .modulemode   = MODULEMODE_HWCTRL,
+               },
+       },
+};
+
 /*
  * 'dss' class
  *
@@ -2586,6 +2647,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3_main_1 -> tpcc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
+       .master         = &dra7xx_l3_main_1_hwmod,
+       .slave          = &dra7xx_tpcc_hwmod,
+       .clk            = "l3_iclk_div",
+       .user           = OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc0 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
+       .master         = &dra7xx_l3_main_1_hwmod,
+       .slave          = &dra7xx_tptc0_hwmod,
+       .clk            = "l3_iclk_div",
+       .user           = OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
+       .master         = &dra7xx_l3_main_1_hwmod,
+       .slave          = &dra7xx_tptc1_hwmod,
+       .clk            = "l3_iclk_div",
+       .user           = OCP_USER_MPU,
+};
+
 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
        {
                .name           = "family",
@@ -3403,6 +3488,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
        &dra7xx_l3_main_1__mcasp3,
        &dra7xx_gmac__mdio,
        &dra7xx_l4_cfg__dma_system,
+       &dra7xx_l3_main_1__tpcc,
+       &dra7xx_l3_main_1__tptc0,
+       &dra7xx_l3_main_1__tptc1,
        &dra7xx_l3_main_1__dss,
        &dra7xx_l3_main_1__dispc,
        &dra7xx_l3_main_1__hdmi,