clk/zynq/pll: Use #defines for fbdiv min/max values

Use more descriptive #defines for the minimum and maximum PLL
feedback divider.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
index 6daa7b6702ed91219ea4a332ba6dbb32f9ad7598..3226f54fa5956a357104f3f8675779179067b717 100644 (file)
--- a/drivers/clk/zynq/pll.c
+++ b/drivers/clk/zynq/pll.c
@@ -50,6 +50,9 @@ struct zynq_pll {
 #define PLLCTRL_RESET_MASK     1
 #define PLLCTRL_RESET_SHIFT    0
 
+#define PLL_FBDIV_MIN  13
+#define PLL_FBDIV_MAX  66
+
 /**
  * zynq_pll_round_rate() - Round a clock frequency
  * @hw:                Handle between common and hardware-specific interfaces
@@ -63,10 +66,10 @@ static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
        u32 fbdiv;
 
        fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
-       if (fbdiv < 13)
-               fbdiv = 13;
-       else if (fbdiv > 66)
-               fbdiv = 66;
+       if (fbdiv < PLL_FBDIV_MIN)
+               fbdiv = PLL_FBDIV_MIN;
+       else if (fbdiv > PLL_FBDIV_MAX)
+               fbdiv = PLL_FBDIV_MAX;
 
        return *prate * fbdiv;
 }