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clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
author
Xing Zheng
<zhengxing@rock-chips.com>
Thu, 30 Jun 2016 02:18:59 +0000
(10:18 +0800)
committer
Heiko Stuebner
<heiko@sntech.de>
Thu, 30 Jun 2016 23:50:17 +0000
(
01:50
+0200)
The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.
Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3399.c
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diff --git
a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index b6742fad3f8d7de4e31f265706e1aba5c89b7145..78e51cb255fb5d71ecc1825bef2382ccd1dc82a0 100644
(file)
--- a/
drivers/clk/rockchip/clk-rk3399.c
+++ b/
drivers/clk/rockchip/clk-rk3399.c
@@
-586,7
+586,7
@@
static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(8), 15, GFLAGS),
COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
- RK3399_CLKSEL_CON(32), 15, 1, MFLAGS,
0
, 5, DFLAGS,
+ RK3399_CLKSEL_CON(32), 15, 1, MFLAGS,
8
, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 6, GFLAGS),
/* i2s */
COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
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