arm: dt: zynq: Add fclk-enable property to clkc node

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 8b67b19392eca7ac1359dfe1db0ec4a16e5d1ade..93d1980a755d8653370f91c116144c99e9fbec00 100644 (file)
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -134,6 +134,7 @@
                                        #clock-cells = <1>;
                                        compatible = "xlnx,ps7-clkc";
                                        ps-clk-frequency = <33333333>;
+                                       fclk-enable = <0>;
                                        clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                                        "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
                                                        "dci", "lqspi", "smc", "pcap", "gem0", "gem1",