* v850-opc.c (v850_operands): "not" is a two byte insn.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a66d07a23bede4c7fb770b216a1373d8abacada0..4ddc4025cd30053ea7cc39b7d4e7c670e6bb1921 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,6 +1,8 @@
 start-sanitize-v850
 Fri Aug 23 00:27:01 1996  Jeffrey A Law  (law@cygnus.com)
 
+       * v850-opc.c (v850_operands): "not" is a two byte insn
+
        * v850-opc.c (v850_opcodes): Correct bit pattern for setf.
 
        * v850-opc.c (v850_operands): D16 inserts at offset 16!

diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index 3d4973ece3e27248a83c10aa4aef190cc0986922..2bb8c07d0a3f501e38da91102ac309a6045e67fd 100644 (file)
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -176,7 +176,7 @@ const struct v850_opcode v850_opcodes[] = {
 { "andi",      OP(0x36),               OP_MASK,        IF6, 4 },
 { "xor",       OP(0x09),               OP_MASK,        IF1, 2 },
 { "xori",      OP(0x35),               OP_MASK,        IF6, 4 },
-{ "not",       OP(0x01),               OP_MASK,        IF1, 4 },
+{ "not",       OP(0x01),               OP_MASK,        IF1, 2 },
 { "sar",       OP(0x15),               OP_MASK,        {I5U, R2}, 2 },
 { "sar",       two(0x07e0,0x00a0),     two(0x07e0,0xffff),     {R1,R2}, 4 },
 { "shl",       OP(0x16),               OP_MASK,                {I5U, R2}, 2 },