RISC-V: Don't generate the ELF privilege attributes when no CSR are used.

	gas/
	* config/tc-riscv.c (explicit_csr): New static boolean.
	Used to indicate CSR are explictly used.
	(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
	(riscv_write_out_attrs): If we already have set elf priv
	attributes, then generate them.  Otherwise, don't generate
	them when no CSR are used.

	* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-11.s: New testcase.
	* testsuite/gas/riscv/attribute-11.d: New testcase.  The CSR is
	used, so we should output the ELF priv attributes.
	* testsuite/gas/riscv/attribute-12.d: New testcase.  The CSR is
	used, so output the priv attributes according to the -mpriv-spec.
	* testsuite/gas/riscv/attribute-13.d: New testcase.  The CSR isn't
	used, so ignore the -mpriv-spec setting.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
	* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 19cefba5e628b7d5501b9a106d1dac8dce5a6003..14d10799f0b9aa199bdc7a061eff523a7a05b6a7 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,30 @@
+2020-06-05  Nelson Chu  <nelson.chu@sifive.com>
+
+       * config/tc-riscv.c (explicit_csr): New static boolean.
+       Used to indicate CSR are explictly used.
+       (riscv_ip): Set explicit_csr to TRUE if any CSR is used.
+       (riscv_write_out_attrs): If we already have set elf priv
+       attributes, then generate them.  Otherwise, don't generate
+       them when no CSR are used.
+       * testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
+       * testsuite/gas/riscv/attribute-02.d: Likewise.
+       * testsuite/gas/riscv/attribute-03.d: Likewise.
+       * testsuite/gas/riscv/attribute-04.d: Likewise.
+       * testsuite/gas/riscv/attribute-05.d: Likewise.
+       * testsuite/gas/riscv/attribute-06.d: Likewise.
+       * testsuite/gas/riscv/attribute-07.d: Likewise.
+       * testsuite/gas/riscv/attribute-08.d: Likewise.
+       * testsuite/gas/riscv/attribute-09.d: Likewise.
+       * testsuite/gas/riscv/attribute-10.d: Likewise.
+       * testsuite/gas/riscv/attribute-unknown.d: Likewise.
+       * testsuite/gas/riscv/attribute-11.s: New testcase.
+       * testsuite/gas/riscv/attribute-11.d: New testcase.  The CSR is
+       used, so we should output the ELF priv attributes.
+       * testsuite/gas/riscv/attribute-12.d: New testcase.  The CSR is
+       used, so output the priv attributes according to the -mpriv-spec.
+       * testsuite/gas/riscv/attribute-13.d: New testcase.  The CSR isn't
+       used, so ignore the -mpriv-spec setting.
+
 2020-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 
        * config/tc-ip2k. (ip2k_apply_fix): Pass endianness to

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index da94b5b1cfba1dbe96a17a92e7034b7c3896a912..cc77dbf6c00a3c9fe769da654b657e0d276d6736 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -374,6 +374,9 @@ static bfd_boolean start_assemble = FALSE;
 /* Indicate ELF attributes are explictly set.  */
 static bfd_boolean explicit_attr = FALSE;
 
+/* Indicate CSR are explictly used.  */
+static bfd_boolean explicit_csr = FALSE;
+
 /* Macros for encoding relaxation state for RVC branches and far jumps.  */
 #define RELAX_BRANCH_ENCODE(uncond, rvc, length)       \
   ((relax_substateT)                                   \
@@ -2212,6 +2215,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 
            case 'E':           /* Control register.  */
              insn_with_csr = TRUE;
+             explicit_csr = TRUE;
              if (reg_lookup (&s, RCLASS_CSR, &regno))
                INSERT_OPERAND (CSR, *ip, regno);
              else
@@ -3605,6 +3609,11 @@ riscv_write_out_attrs (void)
       && !riscv_set_default_priv_spec (NULL))
     return;
 
+  /* If we already have set elf priv attributes, then generate them.
+     Otherwise, don't generate them when no CSR are used.  */
+  if (!explicit_csr)
+    return;
+
   /* Re-write priv attributes by default_priv_spec.  */
   priv_str = riscv_get_priv_spec_name (default_priv_spec);
   p = priv_str;

diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d
index f02734744e1a9549fa89ca9a7d719e2d153166dc..2e19e09abf29eb413af405917e1aa76a4f3ec748 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-01.d
+++ b/gas/testsuite/gas/riscv/attribute-01.d
@@ -4,6 +4,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
index 02b532d0a88c92703bd0877f5f6f0f0d2296e7a0..ae0195e9a2ca69fd6b2031b118b4234125a13960 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-02.d
+++ b/gas/testsuite/gas/riscv/attribute-02.d
@@ -4,6 +4,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
index ded529aa61768088f9e1eecba801677b965fd5be..9916ff6e927a3773aea8be7c247dfc1dd23d09b6 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-03.d
+++ b/gas/testsuite/gas/riscv/attribute-03.d
@@ -4,6 +4,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d
index df6c8182d5b96650d6b17b0d3460306a85185b4a..408464d01ce07673b8a6e2f1d4711558311e6b55 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-04.d
+++ b/gas/testsuite/gas/riscv/attribute-04.d
@@ -4,6 +4,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/gas/testsuite/gas/riscv/attribute-06.d b/gas/testsuite/gas/riscv/attribute-06.d
index e1d62c45db76709657555a2136e2beb1bb5c0ed1..a2dd9fbb97ed5d29628fee74fa0e00f6783a29cb 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-06.d
+++ b/gas/testsuite/gas/riscv/attribute-06.d
@@ -4,6 +4,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/gas/testsuite/gas/riscv/attribute-07.d b/gas/testsuite/gas/riscv/attribute-07.d
index 59f02b4c4e3526e00b7acf5486cb72d7ea827608..342a53752ce61f12669a809138763bd9c9f2fb6e 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-07.d
+++ b/gas/testsuite/gas/riscv/attribute-07.d
@@ -4,6 +4,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv64i2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/gas/testsuite/gas/riscv/attribute-08.d b/gas/testsuite/gas/riscv/attribute-08.d
index 13b82a97a63aee118ae6816f3040d94c248b44e5..c10ac0ca353b489e04b10379a89593c150c6c740 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-08.d
+++ b/gas/testsuite/gas/riscv/attribute-08.d
@@ -4,6 +4,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32e1p9"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
index 53945a27ebc0611d788ee9d69bc39686ea70c2e1..cad1713b0a0af579236346a350455b83d5a55755 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-09.d
+++ b/gas/testsuite/gas/riscv/attribute-09.d
@@ -4,6 +4,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d
index 91691fda77a8b4bf8e06edccc8c4004bec1c53e9..ba903d172750624ada4bef1ee1e38fb408c46915 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-10.d
+++ b/gas/testsuite/gas/riscv/attribute-10.d
@@ -4,6 +4,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/gas/testsuite/gas/riscv/attribute-11.d b/gas/testsuite/gas/riscv/attribute-11.d
new file mode 100644 (file)
index 0000000..4bd66f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-11.d
@@ -0,0 +1,8 @@
+#as: -march-attr
+#readelf: -A
+#source: attribute-11.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+  Tag_RISCV_priv_spec: [0-9_\"].*
+#...

diff --git a/gas/testsuite/gas/riscv/attribute-11.s b/gas/testsuite/gas/riscv/attribute-11.s
new file mode 100644 (file)
index 0000000..81099b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-11.s
@@ -0,0 +1 @@
+       csrr a0, 0x0

diff --git a/gas/testsuite/gas/riscv/attribute-12.d b/gas/testsuite/gas/riscv/attribute-12.d
new file mode 100644 (file)
index 0000000..980b36c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-12.d
@@ -0,0 +1,9 @@
+#as: -march-attr -mpriv-spec=1.9.1
+#readelf: -A
+#source: attribute-11.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+  Tag_RISCV_priv_spec: 1
+  Tag_RISCV_priv_spec_minor: 9
+  Tag_RISCV_priv_spec_revision: 1

diff --git a/gas/testsuite/gas/riscv/attribute-13.d b/gas/testsuite/gas/riscv/attribute-13.d
new file mode 100644 (file)
index 0000000..b8dfe3a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-13.d
@@ -0,0 +1,6 @@
+#as: -march-attr -mpriv-spec=1.9.1
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*

diff --git a/gas/testsuite/gas/riscv/attribute-unknown.d b/gas/testsuite/gas/riscv/attribute-unknown.d
index 120e3dee6ca740312de6dd3eaba3f338e1ce4a9d..667f21acfc1dd9c34ed76657d8bbef8e6185936d 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-unknown.d
+++ b/gas/testsuite/gas/riscv/attribute-unknown.d
@@ -4,8 +4,5 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
   Tag_unknown_255: "test"
   Tag_unknown_256: 123 \(0x7b\)

diff --git a/ld/ChangeLog b/ld/ChangeLog
index 00066c59c07a987f25b3d32ba8d8eff40769ba00..5b6805a31bc4a17b41c4f618716428aa2a487957 100644 (file)
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,17 @@
+2020-06-05  Nelson Chu  <nelson.chu@sifive.com>
+
+       * testsuite/ld-riscv-elf/attr-merge-arch-01.d: The CSR isn't used,
+       so ignore the -mpriv-spec setting.
+       * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
+       * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
+       * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
+       * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
+       * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
+       * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
+       * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
+       * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
+       * testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
+
 2020-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/26080

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index 032f9641ad23dbac98f091f6031e2638d2f9eb41..5baaba4c16f9545cd25dfd59fadfbbf0869dedeb 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -7,6 +7,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_m2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index 54a7621f2c378b948df46876f332adb17439e969..a7d79a1ea2bf7bf0dd44eb3105228a7e8dcdd555 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -7,6 +7,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_m2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index 67f0437e32875e72124e6e1192ca6b55e284cd28..d46dee808de3637e268c0014e6b304ee23e8d4a0 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -7,6 +7,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
index 5585fac3b7b96a3e7bed24a80962ec8696ab6332..e4d965a3e996613c23224ca1ec94841192578726 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
@@ -8,6 +8,4 @@ Attribute Section: riscv
 File Attributes
   Tag_RISCV_stack_align: 16-bytes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
 #...

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
index 91011a2ba4ddf934337adf55668f5cedcfa4f348..10399307bbbe8d9a72b28d0fbf018832350ad424 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
   Tag_RISCV_unaligned_access: Unaligned access
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
index 5bdea27948b6e621ae0ec38f7c9d5adb0fd8e1e5..12ca1c4dd31a294c96025537b618ddfed16c9e48 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
   Tag_RISCV_unaligned_access: Unaligned access
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
index ac886fb768180a1166527c478cc5288ae0f2fac4..e41351da0112b5d96e241778006afd3fe449e88b 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
   Tag_RISCV_unaligned_access: Unaligned access
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
index dd45f76317ad82cec81c710e6eab86d275454710..ac2a766cfcaaea2ac0cd56cfa71bd6911e8f5958 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
@@ -7,6 +7,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
index ef0c154a1210da8e04f3665f51d836f94b3ba4c8..608c05e8c38b12466eb82a330d054e7bbce45c96 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
   Tag_RISCV_unaligned_access: Unaligned access
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...

diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
index 46d9c84f35f75a94ed54537c81eaa0a8f1768104..597ff67535353415653fa3942459b096298b2163 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/call-relax.d
+++ b/ld/testsuite/ld-riscv-elf/call-relax.d
@@ -3,7 +3,7 @@
 #source: call-relax-1.s
 #source: call-relax-2.s
 #source: call-relax-3.s
-#as: -march=rv32ic
+#as: -march=rv32ic -mno-arch-attr
 #ld: -melf32lriscv
 #objdump: -d
 #pass