x86: Add {disp16} pseudo prefix

Use Prefix_XXX for pseudo prefixes.  Add {disp16} pseudo prefix and
replace {disp32} pseudo prefix with {disp16} in 16-bit mode test.
Check invalid {disp16}/{disp32} pseudo prefixes.

gas/

	PR gas/26305
	* config/tc-i386.c (_i386_insn::disp_encoding): Add
	disp_encoding_16bit.
	(parse_insn): Check Prefix_XXX for pseudo prefixes.  Handle
	{disp16}.
	(build_modrm_byte): Handle {disp16}.
	(i386_index_check): Check invalid {disp16} and {disp32} pseudo
	prefixes.
	* doc/c-i386.texi: Update {disp32} documentation and document
	{disp16}.
	* testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo.
	* testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16}
	tests.
	* testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps
	tests with 128-byte displacement.  Add {disp16} tests.
	* testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32}
	vmovaps test.  Add (%r13)/(%r13d) tests.
	* testsuite/gas/i386/x86-64-inval-pseudo.l: New file.
	* testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise.
	* testsuite/gas/i386/inval-pseudo.l: Updated.
	* testsuite/gas/i386/pseudos.d: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.

opcodes/

	PR gas/26305
	* i386-opc.h (Prefix_Disp8): New.
	(Prefix_Disp16): Likewise.
	(Prefix_Disp32): Likewise.
	(Prefix_Load): Likewise.
	(Prefix_Store): Likewise.
	(Prefix_VEX): Likewise.
	(Prefix_VEX3): Likewise.
	(Prefix_EVEX): Likewise.
	(Prefix_REX): Likewise.
	(Prefix_NoOptimize): Likewise.
	* i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
	* i386-tbl.h: Regenerated.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5fd5779a605819dad2443416996ed742d7e71cbd..8dee8190b05f66337de303e4bdf306293e8f23f8 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,28 @@
+2020-07-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/26305
+       * config/tc-i386.c (_i386_insn::disp_encoding): Add
+       disp_encoding_16bit.
+       (parse_insn): Check Prefix_XXX for pseudo prefixes.  Handle
+       {disp16}.
+       (build_modrm_byte): Handle {disp16}.
+       (i386_index_check): Check invalid {disp16} and {disp32} pseudo
+       prefixes.
+       * doc/c-i386.texi: Update {disp32} documentation and document
+       {disp16}.
+       * testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo.
+       * testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16}
+       tests.
+       * testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps
+       tests with 128-byte displacement.  Add {disp16} tests.
+       * testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32}
+       vmovaps test.  Add (%r13)/(%r13d) tests.
+       * testsuite/gas/i386/x86-64-inval-pseudo.l: New file.
+       * testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise.
+       * testsuite/gas/i386/inval-pseudo.l: Updated.
+       * testsuite/gas/i386/pseudos.d: Likewise.
+       * testsuite/gas/i386/x86-64-pseudos.d: Likewise.
+
 2020-07-30  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
        * Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 11d0e992f970fc80ffde7be0247afe8da1363df3..7c21df8d9ace9110f46373cf2fce990c21b37f2a 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -409,11 +409,12 @@ struct _i386_insn
        dir_encoding_swap
       } dir_encoding;
 
-    /* Prefer 8bit or 32bit displacement in encoding.  */
+    /* Prefer 8bit, 16bit, 32bit displacement in encoding.  */
     enum
       {
        disp_encoding_default = 0,
        disp_encoding_8bit,
+       disp_encoding_16bit,
        disp_encoding_32bit
       } disp_encoding;
 
@@ -5119,39 +5120,43 @@ parse_insn (char *line, char *mnemonic)
              /* Handle pseudo prefixes.  */
              switch (current_templates->start->base_opcode)
                {
-               case 0x0:
+               case Prefix_Disp8:
                  /* {disp8} */
                  i.disp_encoding = disp_encoding_8bit;
                  break;
-               case 0x1:
+               case Prefix_Disp16:
+                 /* {disp16} */
+                 i.disp_encoding = disp_encoding_16bit;
+                 break;
+               case Prefix_Disp32:
                  /* {disp32} */
                  i.disp_encoding = disp_encoding_32bit;
                  break;
-               case 0x2:
+               case Prefix_Load:
                  /* {load} */
                  i.dir_encoding = dir_encoding_load;
                  break;
-               case 0x3:
+               case Prefix_Store:
                  /* {store} */
                  i.dir_encoding = dir_encoding_store;
                  break;
-               case 0x4:
+               case Prefix_VEX:
                  /* {vex} */
                  i.vec_encoding = vex_encoding_vex;
                  break;
-               case 0x5:
+               case Prefix_VEX3:
                  /* {vex3} */
                  i.vec_encoding = vex_encoding_vex3;
                  break;
-               case 0x6:
+               case Prefix_EVEX:
                  /* {evex} */
                  i.vec_encoding = vex_encoding_evex;
                  break;
-               case 0x7:
+               case Prefix_REX:
                  /* {rex} */
                  i.rex_encoding = TRUE;
                  break;
-               case 0x8:
+               case Prefix_NoOptimize:
                  /* {nooptimize} */
                  i.no_optimize = TRUE;
                  break;
@@ -8151,9 +8156,7 @@ build_modrm_byte (void)
                      if (operand_type_check (i.types[op], disp) == 0)
                        {
                          /* fake (%bp) into 0(%bp)  */
-                         if (i.disp_encoding == disp_encoding_32bit)
-                           /* NB: Use disp16 since there is no disp32
-                              in 16-bit mode.  */
+                         if (i.disp_encoding == disp_encoding_16bit)
                            i.types[op].bitfield.disp16 = 1;
                          else
                            i.types[op].bitfield.disp8 = 1;
@@ -8166,6 +8169,16 @@ build_modrm_byte (void)
                default: /* (%si) -> 4 or (%di) -> 5  */
                  i.rm.regmem = i.base_reg->reg_num - 6 + 4;
                }
+             if (!fake_zero_displacement
+                 && !i.disp_operands
+                 && i.disp_encoding)
+               {
+                 fake_zero_displacement = 1;
+                 if (i.disp_encoding == disp_encoding_8bit)
+                   i.types[op].bitfield.disp8 = 1;
+                 else
+                   i.types[op].bitfield.disp16 = 1;
+               }
              i.rm.mode = mode_from_disp_size (i.types[op]);
            }
          else /* i.base_reg and 32/64 bit mode  */
@@ -11012,6 +11025,14 @@ i386_index_check (const char *operand_string)
       if (addr_mode != CODE_16BIT)
        {
          /* 32-bit/64-bit checks.  */
+         if (i.disp_encoding == disp_encoding_16bit)
+           {
+           bad_disp:
+             as_bad (_("invalid `%s' prefix"),
+                     addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}");
+             return 0;
+           }
+
          if ((i.base_reg
               && ((addr_mode == CODE_64BIT
                    ? !i.base_reg->reg_type.bitfield.qword
@@ -11049,6 +11070,9 @@ i386_index_check (const char *operand_string)
       else
        {
          /* 16-bit checks.  */
+         if (i.disp_encoding == disp_encoding_32bit)
+           goto bad_disp;
+
          if ((i.base_reg
               && (!i.base_reg->reg_type.bitfield.word
                   || !i.base_reg->reg_type.bitfield.baseindex))

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 8be708e7450ad23bc64a89dc10b6564f2d2c029d..64a563aacb43d39ec872c746bdb715d905695d4f 100644 (file)
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -822,7 +822,10 @@ Different encoding options can be specified via pseudo prefixes:
 @samp{@{disp8@}} -- prefer 8-bit displacement.
 
 @item
-@samp{@{disp32@}} -- prefer 32-bit (16-bit in 16-bit mode) displacement.
+@samp{@{disp32@}} -- prefer 32-bit displacement.
+
+@item
+@samp{@{disp16@}} -- prefer 16-bit displacement.
 
 @item
 @samp{@{load@}} -- prefer load-form instruction.

diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 0ac9c1f129b1b2eefd2f9f00fbd0e5346165c8d5..0a863ff3bd4927025cfda41df7ac624d282af6f1 100644 (file)
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1105,6 +1105,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_list_test "x86-64-cet-shstk-inval"
     run_dump_test "x86-64-pseudos"
     run_list_test "x86-64-pseudos-bad"
+    run_list_test "x86-64-inval-pseudo" "-al"
     run_dump_test "x86-64-notrack"
     run_dump_test "x86-64-notrack-intel"
     run_list_test "x86-64-notrackbad" "-al"

diff --git a/gas/testsuite/gas/i386/inval-pseudo.l b/gas/testsuite/gas/i386/inval-pseudo.l
index cf344f6986b6fed8e620ccdbe055ba6bf51e0a92..9df0a9851fd5e5e90df63872b99095654843c581 100644 (file)
--- a/gas/testsuite/gas/i386/inval-pseudo.l
+++ b/gas/testsuite/gas/i386/inval-pseudo.l
@@ -1,5 +1,7 @@
 .*: Assembler messages:
 .*:3: Error: .*
+.*:5: Error: .*
+.*:6: Error: .*
 GAS LISTING .*
 
 
@@ -7,5 +9,7 @@ GAS LISTING .*
 [      ]*2[    ]+\?\?\?\? 90                   nop
 [      ]*3[    ]+\{disp32\}
 [      ]*4[    ]+\?\?\?\? 90                   nop
-[      ]*5[    ]+\?\?\?\? 00000000             \.p2align 4,0
+[      ]*5[    ]+\{disp32\} movb \(%bp\),%al
+[      ]*6[    ]+\{disp16\} movb \(%ebp\),%al
+[      ]*7[    ]+\?\?\?\? 00000000             \.p2align 4,0
 #...

diff --git a/gas/testsuite/gas/i386/inval-pseudo.s b/gas/testsuite/gas/i386/inval-pseudo.s
index a40362b8f956adc2e98b99283c462087e5a3f2de..b5a6233eb1d4dd68acfb86450a114795ff28bbaa 100644 (file)
--- a/gas/testsuite/gas/i386/inval-pseudo.s
+++ b/gas/testsuite/gas/i386/inval-pseudo.s
@@ -2,4 +2,6 @@
        nop
        {disp32}
        nop
+       {disp32} movb (%bp),%al
+       {disp16} movb (%ebp),%al
        .p2align 4,0

diff --git a/gas/testsuite/gas/i386/pseudos.d b/gas/testsuite/gas/i386/pseudos.d
index 76aae367b446ab37cfdc2c891bc2bda67a9d2f1b..4f029f154b45b8bcfd7c2794a719cc5ac5e6d3bd 100644 (file)
--- a/gas/testsuite/gas/i386/pseudos.d
+++ b/gas/testsuite/gas/i386/pseudos.d
@@ -22,6 +22,10 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f8 28 90 00 00 00 00         vmovaps 0x0\(%eax\),%xmm2
  +[a-f0-9]+:   62 f1 7c 08 28 50 00    vmovaps 0x0\(%eax\),%xmm2
  +[a-f0-9]+:   62 f1 7c 08 28 90 00 00 00 00   vmovaps 0x0\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f8 28 90 80 00 00 00         vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f8 28 90 80 00 00 00         vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+:   62 f1 7c 08 28 50 08    vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+:   62 f1 7c 08 28 90 80 00 00 00   vmovaps 0x80\(%eax\),%xmm2
  +[a-f0-9]+:   89 c8                   mov    %ecx,%eax
  +[a-f0-9]+:   8b c1                   mov    %ecx,%eax
  +[a-f0-9]+:   89 c8                   mov    %ecx,%eax
@@ -291,9 +295,15 @@ Disassembly of section .text:
  +[a-f0-9]+:   8a 45 00                mov    0x0\(%ebp\),%al
  +[a-f0-9]+:   8a 45 00                mov    0x0\(%ebp\),%al
  +[a-f0-9]+:   8a 85 00 00 00 00       mov    0x0\(%ebp\),%al
+ +[a-f0-9]+:   67 8a 04                mov    \(%si\),%al
+ +[a-f0-9]+:   67 8a 44 00             mov    0x0\(%si\),%al
+ +[a-f0-9]+:   67 8a 84 00 00          mov    0x0\(%si\),%al
+ +[a-f0-9]+:   67 8a 05                mov    \(%di\),%al
+ +[a-f0-9]+:   67 8a 45 00             mov    0x0\(%di\),%al
+ +[a-f0-9]+:   67 8a 85 00 00          mov    0x0\(%di\),%al
  +[a-f0-9]+:   67 8a 07                mov    \(%bx\),%al
- +[a-f0-9]+:   67 8a 07                mov    \(%bx\),%al
- +[a-f0-9]+:   67 8a 07                mov    \(%bx\),%al
+ +[a-f0-9]+:   67 8a 47 00             mov    0x0\(%bx\),%al
+ +[a-f0-9]+:   67 8a 87 00 00          mov    0x0\(%bx\),%al
  +[a-f0-9]+:   67 8a 46 00             mov    0x0\(%bp\),%al
  +[a-f0-9]+:   67 8a 46 00             mov    0x0\(%bp\),%al
  +[a-f0-9]+:   67 8a 86 00 00          mov    0x0\(%bp\),%al
@@ -311,6 +321,10 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f8 28 90 00 00 00 00         vmovaps 0x0\(%eax\),%xmm2
  +[a-f0-9]+:   62 f1 7c 08 28 50 00    vmovaps 0x0\(%eax\),%xmm2
  +[a-f0-9]+:   62 f1 7c 08 28 90 00 00 00 00   vmovaps 0x0\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f8 28 90 80 00 00 00         vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+:   c5 f8 28 90 80 00 00 00         vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+:   62 f1 7c 08 28 50 08    vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+:   62 f1 7c 08 28 90 80 00 00 00   vmovaps 0x80\(%eax\),%xmm2
  +[a-f0-9]+:   89 c8                   mov    %ecx,%eax
  +[a-f0-9]+:   8b c1                   mov    %ecx,%eax
  +[a-f0-9]+:   89 c8                   mov    %ecx,%eax
@@ -328,9 +342,15 @@ Disassembly of section .text:
  +[a-f0-9]+:   8a 45 00                mov    0x0\(%ebp\),%al
  +[a-f0-9]+:   8a 45 00                mov    0x0\(%ebp\),%al
  +[a-f0-9]+:   8a 85 00 00 00 00       mov    0x0\(%ebp\),%al
+ +[a-f0-9]+:   67 8a 04                mov    \(%si\),%al
+ +[a-f0-9]+:   67 8a 44 00             mov    0x0\(%si\),%al
+ +[a-f0-9]+:   67 8a 84 00 00          mov    0x0\(%si\),%al
+ +[a-f0-9]+:   67 8a 05                mov    \(%di\),%al
+ +[a-f0-9]+:   67 8a 45 00             mov    0x0\(%di\),%al
+ +[a-f0-9]+:   67 8a 85 00 00          mov    0x0\(%di\),%al
  +[a-f0-9]+:   67 8a 07                mov    \(%bx\),%al
- +[a-f0-9]+:   67 8a 07                mov    \(%bx\),%al
- +[a-f0-9]+:   67 8a 07                mov    \(%bx\),%al
+ +[a-f0-9]+:   67 8a 47 00             mov    0x0\(%bx\),%al
+ +[a-f0-9]+:   67 8a 87 00 00          mov    0x0\(%bx\),%al
  +[a-f0-9]+:   67 8a 46 00             mov    0x0\(%bp\),%al
  +[a-f0-9]+:   67 8a 46 00             mov    0x0\(%bp\),%al
  +[a-f0-9]+:   67 8a 86 00 00          mov    0x0\(%bp\),%al

diff --git a/gas/testsuite/gas/i386/pseudos.s b/gas/testsuite/gas/i386/pseudos.s
index bc18654ced037e00e57dad3d065059e5fe1b031c..603e112ac8ed6660d1d181a37ed0f63b35beaca0 100644 (file)
--- a/gas/testsuite/gas/i386/pseudos.s
+++ b/gas/testsuite/gas/i386/pseudos.s
@@ -17,6 +17,11 @@ _start:
        {evex} {disp8} vmovaps (%eax),%xmm2
        {evex} {disp32} vmovaps (%eax),%xmm2
 
+       {vex} {disp8} vmovaps 128(%eax),%xmm2
+       {vex} {disp32} vmovaps 128(%eax),%xmm2
+       {evex} {disp8} vmovaps 128(%eax),%xmm2
+       {evex} {disp32} vmovaps 128(%eax),%xmm2
+
        mov %ecx, %eax
        {load} mov %ecx, %eax
        {store} mov %ecx, %eax
@@ -297,13 +302,21 @@ _start:
        {disp8} movb (%ebp),%al
        {disp32} movb (%ebp),%al
 
+       movb (%si),%al
+       {disp8} movb (%si),%al
+       {disp16} movb (%si),%al
+
+       movb (%di),%al
+       {disp8} movb (%di),%al
+       {disp16} movb (%di),%al
+
        movb (%bx),%al
        {disp8} movb (%bx),%al
-       {disp32} movb (%bx),%al
+       {disp16} movb (%bx),%al
 
        movb (%bp),%al
        {disp8} movb (%bp),%al
-       {disp32} movb (%bp),%al
+       {disp16} movb (%bp),%al
 
        .intel_syntax noprefix
        {vex3} vmovaps xmm2,xmm7
@@ -320,6 +333,12 @@ _start:
        {disp32} vmovaps xmm2,XMMWORD PTR [eax]
        {evex} {disp8} vmovaps xmm2,XMMWORD PTR [eax]
        {evex} {disp32} vmovaps xmm2,XMMWORD PTR [eax]
+
+       {vex} {disp8} vmovaps xmm2,XMMWORD PTR [eax+128]
+       {vex} {disp32} vmovaps xmm2,XMMWORD PTR [eax+128]
+       {evex} {disp8} vmovaps xmm2,XMMWORD PTR [eax+128]
+       {evex} {disp32} vmovaps xmm2,XMMWORD PTR [eax+128]
+
        mov eax,ecx
        {load} mov eax,ecx
        {store} mov eax,ecx
@@ -339,10 +358,18 @@ _start:
        {disp8} mov al, BYTE PTR [ebp]
        {disp32} mov al, BYTE PTR [ebp]
 
+       mov al, BYTE PTR [si]
+       {disp8} mov al, BYTE PTR [si]
+       {disp16} mov al, BYTE PTR [si]
+
+       mov al, BYTE PTR [di]
+       {disp8} mov al, BYTE PTR [di]
+       {disp16} mov al, BYTE PTR [di]
+
        mov al, BYTE PTR [bx]
        {disp8} mov al, BYTE PTR [bx]
-       {disp32} mov al, BYTE PTR [bx]
+       {disp16} mov al, BYTE PTR [bx]
 
        mov al, BYTE PTR [bp]
        {disp8} mov al, BYTE PTR [bp]
-       {disp32} mov al, BYTE PTR [bp]
+       {disp16} mov al, BYTE PTR [bp]

diff --git a/gas/testsuite/gas/i386/x86-64-inval-pseudo.l b/gas/testsuite/gas/i386/x86-64-inval-pseudo.l
new file mode 100644 (file)
index 0000000..13ad0fb
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-inval-pseudo.l
@@ -0,0 +1,10 @@
+.*: Assembler messages:
+.*:2: Error: .*
+.*:3: Error: .*
+GAS LISTING .*
+
+
+[      ]*1[    ]+\.text
+[      ]*2[    ]+\{disp16\} movb \(%ebp\),%al
+[      ]*3[    ]+\{disp16\} movb \(%rbp\),%al
+#...

diff --git a/gas/testsuite/gas/i386/x86-64-inval-pseudo.s b/gas/testsuite/gas/i386/x86-64-inval-pseudo.s
new file mode 100644 (file)
index 0000000..c10b14c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-inval-pseudo.s
@@ -0,0 +1,4 @@
+       .text
+       {disp16} movb (%ebp),%al
+       {disp16} movb (%rbp),%al
+       .p2align 4,0

diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.d b/gas/testsuite/gas/i386/x86-64-pseudos.d
index 0fb18a33696a389a2b54e6d2e2591e2d2d9eaad6..5d039dc6f9f64c64822b1531360358170ce7e060 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-pseudos.d
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.d
@@ -22,6 +22,10 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f8 28 90 00 00 00 00         vmovaps 0x0\(%rax\),%xmm2
  +[a-f0-9]+:   62 f1 7c 08 28 50 00    vmovaps 0x0\(%rax\),%xmm2
  +[a-f0-9]+:   62 f1 7c 08 28 90 00 00 00 00   vmovaps 0x0\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f8 28 90 80 00 00 00         vmovaps 0x80\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f8 28 90 80 00 00 00         vmovaps 0x80\(%rax\),%xmm2
+ +[a-f0-9]+:   62 f1 7c 08 28 50 08    vmovaps 0x80\(%rax\),%xmm2
+ +[a-f0-9]+:   62 f1 7c 08 28 90 80 00 00 00   vmovaps 0x80\(%rax\),%xmm2
  +[a-f0-9]+:   48 89 c8                mov    %rcx,%rax
  +[a-f0-9]+:   48 8b c1                mov    %rcx,%rax
  +[a-f0-9]+:   48 89 c8                mov    %rcx,%rax
@@ -304,7 +308,7 @@ Disassembly of section .text:
  +[a-f0-9]+:   40 d3 e0                rex shl %cl,%eax
  +[a-f0-9]+:   40 a0 01 00 00 00 00 00 00 00   rex movabs 0x1,%al
  +[a-f0-9]+:   40 38 ca                rex cmp %cl,%dl
- +[a-f0-9]+:   40 b3 01                rex mov \$(0x)?1,%bl
+ +[a-f0-9]+:   40 b3 01                rex mov \$(0x)1,%bl
  +[a-f0-9]+:   f2 40 0f 38 f0 c1       rex crc32 %cl,%eax
  +[a-f0-9]+:   40 89 c3                rex mov %eax,%ebx
  +[a-f0-9]+:   41 89 c6                mov    %eax,%r14d
@@ -321,6 +325,12 @@ Disassembly of section .text:
  +[a-f0-9]+:   67 8a 45 00             mov    0x0\(%ebp\),%al
  +[a-f0-9]+:   67 8a 45 00             mov    0x0\(%ebp\),%al
  +[a-f0-9]+:   67 8a 85 00 00 00 00    mov    0x0\(%ebp\),%al
+ +[a-f0-9]+:   41 8a 45 00             mov    0x0\(%r13\),%al
+ +[a-f0-9]+:   41 8a 45 00             mov    0x0\(%r13\),%al
+ +[a-f0-9]+:   41 8a 85 00 00 00 00    mov    0x0\(%r13\),%al
+ +[a-f0-9]+:   67 41 8a 45 00          mov    0x0\(%r13d\),%al
+ +[a-f0-9]+:   67 41 8a 45 00          mov    0x0\(%r13d\),%al
+ +[a-f0-9]+:   67 41 8a 85 00 00 00 00         mov    0x0\(%r13d\),%al
  +[a-f0-9]+:   c4 e1 78 28 d7          vmovaps %xmm7,%xmm2
  +[a-f0-9]+:   c4 e1 78 28 d7          vmovaps %xmm7,%xmm2
  +[a-f0-9]+:   c4 e1 78 29 fa          vmovaps %xmm7,%xmm2
@@ -335,6 +345,10 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f8 28 90 00 00 00 00         vmovaps 0x0\(%rax\),%xmm2
  +[a-f0-9]+:   62 f1 7c 08 28 50 00    vmovaps 0x0\(%rax\),%xmm2
  +[a-f0-9]+:   62 f1 7c 08 28 90 00 00 00 00   vmovaps 0x0\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f8 28 90 80 00 00 00         vmovaps 0x80\(%rax\),%xmm2
+ +[a-f0-9]+:   c5 f8 28 90 80 00 00 00         vmovaps 0x80\(%rax\),%xmm2
+ +[a-f0-9]+:   62 f1 7c 08 28 50 08    vmovaps 0x80\(%rax\),%xmm2
+ +[a-f0-9]+:   62 f1 7c 08 28 90 80 00 00 00   vmovaps 0x80\(%rax\),%xmm2
  +[a-f0-9]+:   48 89 c8                mov    %rcx,%rax
  +[a-f0-9]+:   48 8b c1                mov    %rcx,%rax
  +[a-f0-9]+:   48 89 c8                mov    %rcx,%rax
@@ -365,4 +379,10 @@ Disassembly of section .text:
  +[a-f0-9]+:   67 8a 45 00             mov    0x0\(%ebp\),%al
  +[a-f0-9]+:   67 8a 45 00             mov    0x0\(%ebp\),%al
  +[a-f0-9]+:   67 8a 85 00 00 00 00    mov    0x0\(%ebp\),%al
+ +[a-f0-9]+:   41 8a 45 00             mov    0x0\(%r13\),%al
+ +[a-f0-9]+:   41 8a 45 00             mov    0x0\(%r13\),%al
+ +[a-f0-9]+:   41 8a 85 00 00 00 00    mov    0x0\(%r13\),%al
+ +[a-f0-9]+:   41 8a 45 00             mov    0x0\(%r13\),%al
+ +[a-f0-9]+:   67 41 8a 45 00          mov    0x0\(%r13d\),%al
+ +[a-f0-9]+:   67 41 8a 85 00 00 00 00         mov    0x0\(%r13d\),%al
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s
index 3b3638cf750e2ebb5b67a0ac3ae70d334eb3e8fb..3818df9708e612849a28e73b990e7864c4fefadf 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-pseudos.s
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.s
@@ -17,6 +17,11 @@ _start:
        {evex} {disp8} vmovaps (%rax),%xmm2
        {evex} {disp32} vmovaps (%rax),%xmm2
 
+       {vex} {disp8} vmovaps 128(%rax),%xmm2
+       {vex} {disp32} vmovaps 128(%rax),%xmm2
+       {evex} {disp8} vmovaps 128(%rax),%xmm2
+       {evex} {disp32} vmovaps 128(%rax),%xmm2
+
        mov %rcx, %rax
        {load} mov %rcx, %rax
        {store} mov %rcx, %rax
@@ -328,6 +333,14 @@ _start:
        {disp8} movb (%ebp),%al
        {disp32} movb (%ebp),%al
 
+       movb (%r13),%al
+       {disp8} movb (%r13),%al
+       {disp32} movb (%r13),%al
+
+       movb (%r13d),%al
+       {disp8} movb (%r13d),%al
+       {disp32} movb (%r13d),%al
+
        .intel_syntax noprefix
        {vex3} vmovaps xmm2,xmm7
        {vex3} {load} vmovaps xmm2,xmm7
@@ -343,6 +356,12 @@ _start:
        {disp32} vmovaps xmm2,XMMWORD PTR [rax]
        {evex} {disp8} vmovaps xmm2,XMMWORD PTR [rax]
        {evex} {disp32} vmovaps xmm2,XMMWORD PTR [rax]
+
+       {vex} {disp8} vmovaps xmm2,XMMWORD PTR [rax+128]
+       {vex} {disp32} vmovaps xmm2,XMMWORD PTR [rax+128]
+       {evex} {disp8} vmovaps xmm2,XMMWORD PTR [rax+128]
+       {evex} {disp32} vmovaps xmm2,XMMWORD PTR [rax+128]
+
        mov rax,rcx
        {load} mov rax,rcx
        {store} mov rax,rcx
@@ -375,3 +394,11 @@ _start:
        mov al, BYTE PTR [ebp]
        {disp8} mov al, BYTE PTR [ebp]
        {disp32} mov al, BYTE PTR [ebp]
+
+       mov al, BYTE PTR [r13]
+       {disp8} mov al, BYTE PTR [r13]
+       {disp32} mov al, BYTE PTR [r13]
+
+       mov al, BYTE PTR [r13]
+       {disp8} mov al, BYTE PTR [r13d]
+       {disp32} mov al, BYTE PTR [r13d]

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4f56e1385bc9d103c7cc48fbab3594d98000b329..3fae7c76cffbbb9a483276cd06857c1ddbbc7357 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,19 @@
+2020-07-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/26305
+       * i386-opc.h (Prefix_Disp8): New.
+       (Prefix_Disp16): Likewise.
+       (Prefix_Disp32): Likewise.
+       (Prefix_Load): Likewise.
+       (Prefix_Store): Likewise.
+       (Prefix_VEX): Likewise.
+       (Prefix_VEX3): Likewise.
+       (Prefix_EVEX): Likewise.
+       (Prefix_REX): Likewise.
+       (Prefix_NoOptimize): Likewise.
+       * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
+       * i386-tbl.h: Regenerated.
+
 2020-07-29  Andreas Arnez  <arnez@linux.ibm.com>
 
        * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index b8a6dfc25c07daf58e3fd3c73ba617ccb7c55546..09ee615db1e67a292f2c287a8e07ef3d276a6734 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -889,6 +889,18 @@ typedef struct insn_template
 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 
+/* Pseudo prefixes.  */
+#define Prefix_Disp8           0       /* {disp8} */
+#define Prefix_Disp16          1       /* {disp16} */
+#define Prefix_Disp32          2       /* {disp32} */
+#define Prefix_Load            3       /* {load} */
+#define Prefix_Store           4       /* {store} */
+#define Prefix_VEX             5       /* {vex} */
+#define Prefix_VEX3            6       /* {vex3} */
+#define Prefix_EVEX            7       /* {evex} */
+#define Prefix_REX             8       /* {rex} */
+#define Prefix_NoOptimize      9       /* {nooptimize} */
+
   /* extension_opcode is the 3 bit extension for group <n> insns.
      This field is also used to store the 8-bit opcode suffix for the
      AMD 3DNow! instructions.

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index bb7fb02dde4d7c7fd1aaeb82be978d90d41dc079..181d0df1ce4abdfcd82b5ef2ba501af09bf7afe2 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -835,16 +835,17 @@ rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
 
 // Pseudo prefixes (opcode_length == 0)
 
-{disp8}, 0, 0x0, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
-{disp32}, 0, 0x1, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
-{load}, 0, 0x2, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
-{store}, 0, 0x3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
-{vex}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
-{vex2}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
-{vex3}, 0, 0x5, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
-{evex}, 0, 0x6, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
-{rex}, 0, 0x7, None, 0, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
-{nooptimize}, 0, 0x8, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{disp8}, 0, Prefix_Disp8, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{disp16}, 0, Prefix_Disp16, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{disp32}, 0, Prefix_Disp32, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{load}, 0, Prefix_Load, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{store}, 0, Prefix_Store, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{vex}, 0, Prefix_VEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{vex2}, 0, Prefix_VEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{vex3}, 0, Prefix_VEX3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{evex}, 0, Prefix_EVEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{rex}, 0, Prefix_REX, None, 0, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{nooptimize}, 0, Prefix_NoOptimize, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
 
 // 486 extensions.
 

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index a3aa69175a3bae2e6606a86acbb25ca7de7d0156..413c730f863cf89bad4bd8e76bd730659fcbf4d1 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -7584,7 +7584,7 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{disp8}", 0x0, None, 0, 0,
+  { "{disp8}", 0, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -7596,7 +7596,7 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{disp32}", 0x1, None, 0, 0,
+  { "{disp16}", 1, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -7608,7 +7608,7 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{load}", 0x2, None, 0, 0,
+  { "{disp32}", 2, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -7620,7 +7620,7 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{store}", 0x3, None, 0, 0,
+  { "{load}", 3, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -7632,7 +7632,7 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{vex}", 0x4, None, 0, 0,
+  { "{store}", 4, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -7644,7 +7644,7 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{vex2}", 0x4, None, 0, 0,
+  { "{vex}", 5, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -7656,7 +7656,7 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{vex3}", 0x5, None, 0, 0,
+  { "{vex2}", 5, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -7668,7 +7668,7 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{evex}", 0x6, None, 0, 0,
+  { "{vex3}", 6, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -7680,7 +7680,19 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{rex}", 0x7, None, 0, 0,
+  { "{evex}", 7, None, 0, 0,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 0, 0, 0, 0, 0 } } } },
+  { "{rex}", 8, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -7692,7 +7704,7 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0 } } } },
-  { "{nooptimize}", 0x8, None, 0, 0,
+  { "{nooptimize}", 9, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,