x86: Add {vex} pseudo prefix

There are 2-byte VEX prefix and 3-byte VEX prefix.  2-byte VEX prefix
can't encode all operands.  By default, assembler tries 2-byte VEX prefix
first.  {vex3} can be used to force 3-byte VEX prefix.  This patch adds
{vex} pseudo prefix and keeps {vex2} for backward compatibility.

gas/

	* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
	with vex_encoding_vex.
	(parse_insn): Likewise.
	* doc/c-i386.texi: Replace {vex2} with {vex}.  Update {vex}
	and {vex3} documentation.
	* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
	{vex}.
	* testsuite/gas/i386/x86-64-pseudos.s: Likewise.

opcodes/

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index f2b49b7a89d1ba9b45d8192768aee5c265a2f88c..e3adaa722acc4e864fcaaeae74c81e78cb39f289 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,14 @@
+2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
+       with vex_encoding_vex.
+       (parse_insn): Likewise.
+       * doc/c-i386.texi: Replace {vex2} with {vex}.  Update {vex}
+       and {vex3} documentation.
+       * testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
+       {vex}.
+       * testsuite/gas/i386/x86-64-pseudos.s: Likewise.
+
 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
        PR 25376

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 3f7f4222bf5f5879e125b72658263624efc83b0c..8728725b82d49bb64d169269167a58fa103827bc 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -419,7 +419,7 @@ struct _i386_insn
     enum
       {
        vex_encoding_default = 0,
-       vex_encoding_vex2,
+       vex_encoding_vex,
        vex_encoding_vex3,
        vex_encoding_evex
       } vec_encoding;
@@ -4722,8 +4722,8 @@ parse_insn (char *line, char *mnemonic)
                  i.dir_encoding = dir_encoding_store;
                  break;
                case 0x4:
-                 /* {vex2} */
-                 i.vec_encoding = vex_encoding_vex2;
+                 /* {vex} */
+                 i.vec_encoding = vex_encoding_vex;
                  break;
                case 0x5:
                  /* {vex3} */

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 4b258030135a2adaf1f23565fc46b86d179d4333..e8685dd046ff74fe1d21a32773bed3aab855e958 100644 (file)
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -758,10 +758,10 @@ Different encoding options can be specified via pseudo prefixes:
 @samp{@{store@}} -- prefer store-form instruction.
 
 @item
-@samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
+@samp{@{vex@}} --  encode with VEX prefix.
 
 @item
-@samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
+@samp{@{vex3@}} -- encode with 3-byte VEX prefix.
 
 @item
 @samp{@{evex@}} --  encode with EVEX prefix.

diff --git a/gas/testsuite/gas/i386/pseudos.s b/gas/testsuite/gas/i386/pseudos.s
index 419a4c51e924cc9d0b81bffa50fb74d6af02da3b..19900dd7e5999b60d1d879644d6ef89ff48d327e 100644 (file)
--- a/gas/testsuite/gas/i386/pseudos.s
+++ b/gas/testsuite/gas/i386/pseudos.s
@@ -6,9 +6,9 @@ _start:
        {vex3} {load} vmovaps %xmm7,%xmm2
        {vex3} {store} vmovaps %xmm7,%xmm2
        vmovaps %xmm7,%xmm2
-       {vex2} vmovaps %xmm7,%xmm2
-       {vex2} {load} vmovaps %xmm7,%xmm2
-       {vex2} {store} vmovaps %xmm7,%xmm2
+       {vex} vmovaps %xmm7,%xmm2
+       {vex} {load} vmovaps %xmm7,%xmm2
+       {vex} {store} vmovaps %xmm7,%xmm2
        {vex3} vmovaps (%eax),%xmm2
        vmovaps (%eax),%xmm2
        {vex2} vmovaps (%eax),%xmm2

diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s
index 33712d3e636d1dcdcdbd66410a35e90a776d8514..14b6c92b864c20b47f613e036dce60a2069cfbff 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-pseudos.s
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.s
@@ -6,9 +6,9 @@ _start:
        {vex3} {load} vmovaps %xmm7,%xmm2
        {vex3} {store} vmovaps %xmm7,%xmm2
        vmovaps %xmm7,%xmm2
-       {vex2} vmovaps %xmm7,%xmm2
-       {vex2} {load} vmovaps %xmm7,%xmm2
-       {vex2} {store} vmovaps %xmm7,%xmm2
+       {vex} vmovaps %xmm7,%xmm2
+       {vex} {load} vmovaps %xmm7,%xmm2
+       {vex} {store} vmovaps %xmm7,%xmm2
        {vex3} vmovaps (%rax),%xmm2
        vmovaps (%rax),%xmm2
        {vex2} vmovaps (%rax),%xmm2

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2d3b6d14401a8187f69b5815461a9639b644814b..e48e566cbc36f16b168c4f9cc3757c2f9f4509c5 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-opc.tbl: Add {vex} pseudo prefix.
+       * i386-tbl.h: Regenerated.
+
 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
        PR 25376

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 73cd6c6a11eb979912a7669c19952c87fbc86e02..d8af259903248565b775a220bc270775eebb3208 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -879,6 +879,7 @@ rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
 {disp32}, 0, 0x1, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
 {load}, 0, 0x2, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
 {store}, 0, 0x3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{vex}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
 {vex2}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
 {vex3}, 0, 0x5, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
 {evex}, 0, 0x6, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index e9381bf11b27d02d6b2f77065ee5c8054d9fb842..758d92bcfd292918f7dce5c6700e4a56ddb9a423 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -7600,6 +7600,18 @@ const insn_template i386_optab[] =
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0 } } } },
+  { "{vex}", 0x4, None, 0, 0,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 0, 0, 0, 0 } } } },
   { "{vex2}", 0x4, None, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,