fsldma: do not clear bandwidth control bits on the 83xx controller

The 83xx controller does not support the external pause feature. The bit
in the mode register that controls external pause on the 85xx controller
happens to be part of the bandwidth control settings for the 83xx
controller.

This patch fixes the driver so that it only clears the external pause bit
if the hardware is the 85xx controller. When driving the 83xx controller,
the bit is left untouched. This follows the existing convention that mode
registers settings are not touched unless necessary.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 10bcf0cb0efcf4cbc99264d06146183da98e1a12..6e60c77a145cf694d297744cc85c1729a8a97c80 100644 (file)
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -147,10 +147,11 @@ static void dma_start(struct fsl_dma_chan *fsl_chan)
        if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
                DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
                mr_set |= FSL_DMA_MR_EMP_EN;
-       } else
+       } else if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
                DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
                        DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
                                & ~FSL_DMA_MR_EMP_EN, 32);
+       }
 
        if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
                mr_set |= FSL_DMA_MR_EMS_EN;