* m10300-opc.c: Add DSP autoincrement memory loads/stores.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 55bd56118445168d8888fef92ca0fc385ff11b5d..ccdf845772330908ba7a8b49d77f76c24fece41d 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,6 +1,8 @@
 start-sanitize-am33
 Thu Jul 23 09:21:03 1998  Jeffrey A Law  (law@cygnus.com)
 
+       * m10300-opc.c: Add DSP autoincrement memory loads/stores.
+
        * m10300-opc.c: Add autoincrement memory loads/stores.
 
 end-sanitize-am33

diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c
index 2c09ff8c52617503214e513456584eb08a22aaaa..6a26130714cd6167e5e7fad7fd91b045ff9ae4b5 100644 (file)
--- a/opcodes/m10300-opc.c
+++ b/opcodes/m10300-opc.c
@@ -1724,6 +1724,50 @@ const struct mn10300_opcode mn10300_opcodes[] = {
                                                          RM6, RN4}},
 { "sub_xor",   0xf73a0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
                                                          RM6, RN4}},
+{ "mov_llt",   0xf7e00000,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "mov_lgt",   0xf7e00001,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "mov_lge",   0xf7e00002,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "mov_lle",   0xf7e00003,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "mov_lcs",   0xf7e00004,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "mov_lhi",   0xf7e00005,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "mov_lcc",   0xf7e00006,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "mov_lls",   0xf7e00007,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "mov_leq",   0xf7e00008,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "mov_lne",   0xf7e00009,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "mov_lra",   0xf7e0000a,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "llt_mov",   0xf7e00000,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "lgt_mov",   0xf7e00001,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "lge_mov",   0xf7e00002,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "lle_mov",   0xf7e00003,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "lcs_mov",   0xf7e00004,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "lhi_mov",   0xf7e00005,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "lcc_mov",   0xf7e00006,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "lls_mov",   0xf7e00007,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "leq_mov",   0xf7e00008,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "lne_mov",   0xf7e00009,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
+{ "lra_mov",   0xf7e0000a,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
+                                                         RM6}},
 /* end-sanitize-am33 */
 
 { 0, 0, 0, 0, 0, {0}},