Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.

opcodes * arm-dis.c (print_insn_arm): Disassembling for all targets V6
	and higher with ARM instruction set will now mark the 26-bit
	versions of teq,tst,cmn and cmp as UNPREDICTABLE.
	(arm_opcodes): Fix for unpredictable nop being recognized as a teq.

test    * gas/arm/nops.d: New.
	* gas/arm/nops.s: New.
	* gas/arm/inst.d: Changed expectation file for 26-bit  teq,
	tst, cmn and cmp.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index f4601b82f127bb4b2faf26ad9d340b9d735e3ab3..b86a46e61ddc2b555f14ca26d54dc4977e1b5bcb 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * gas/arm/nops.d: New.
+       * gas/arm/nops.s: New.
+       * gas/arm/inst.d: Changed expectation file for 26-bit teq,
+       tst, cmn and cmp.
+
 2015-08-12  Max Filippov  <jcmvbkbc@gmail.com>
 
        * gas/xtensa/all.exp: Add auto-litpools to the list of xtensa

diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d
index e298c5fe41b401dcdb3d4ef87da1bdf58786b480..d7ca4a3ce849980a7524c5875a74ca436727993c 100644 (file)
--- a/gas/testsuite/gas/arm/inst.d
+++ b/gas/testsuite/gas/arm/inst.d
@@ -95,22 +95,22 @@ Disassembly of section .text:
 0+14c <[^>]*> e1720004 ?       cmn     r2, r4
 0+150 <[^>]*> e1750287 ?       cmn     r5, r7, lsl #5
 0+154 <[^>]*> e1710113 ?       cmn     r1, r3, lsl r1
-0+158 <[^>]*> e330f00a ?       teq     r0, #10
-0+15c <[^>]*> e132f004 ?       teq     r2, r4
-0+160 <[^>]*> e135f287 ?       teq     r5, r7, lsl #5
-0+164 <[^>]*> e131f113 ?       teq     r1, r3, lsl r1
-0+168 <[^>]*> e370f00a ?       cmn     r0, #10
-0+16c <[^>]*> e172f004 ?       cmn     r2, r4
-0+170 <[^>]*> e175f287 ?       cmn     r5, r7, lsl #5
-0+174 <[^>]*> e171f113 ?       cmn     r1, r3, lsl r1
-0+178 <[^>]*> e350f00a ?       cmp     r0, #10
-0+17c <[^>]*> e152f004 ?       cmp     r2, r4
-0+180 <[^>]*> e155f287 ?       cmp     r5, r7, lsl #5
-0+184 <[^>]*> e151f113 ?       cmp     r1, r3, lsl r1
-0+188 <[^>]*> e310f00a ?       tst     r0, #10
-0+18c <[^>]*> e112f004 ?       tst     r2, r4
-0+190 <[^>]*> e115f287 ?       tst     r5, r7, lsl #5
-0+194 <[^>]*> e111f113 ?       tst     r1, r3, lsl r1
+0+158 <[^>]*> e330f00a ?       teq     r0, #10 ; <UNPREDICTABLE>
+0+15c <[^>]*> e132f004 ?       teq     r2, r4  ; <UNPREDICTABLE>
+0+160 <[^>]*> e135f287 ?       teq     r5, r7, lsl #5  ; <UNPREDICTABLE>
+0+164 <[^>]*> e131f113 ?       teq     r1, r3, lsl r1  ; <UNPREDICTABLE>
+0+168 <[^>]*> e370f00a ?       cmn     r0, #10 ; <UNPREDICTABLE>
+0+16c <[^>]*> e172f004 ?       cmn     r2, r4  ; <UNPREDICTABLE>
+0+170 <[^>]*> e175f287 ?       cmn     r5, r7, lsl #5  ; <UNPREDICTABLE>
+0+174 <[^>]*> e171f113 ?       cmn     r1, r3, lsl r1  ; <UNPREDICTABLE>
+0+178 <[^>]*> e350f00a ?       cmp     r0, #10 ; <UNPREDICTABLE>
+0+17c <[^>]*> e152f004 ?       cmp     r2, r4  ; <UNPREDICTABLE>
+0+180 <[^>]*> e155f287 ?       cmp     r5, r7, lsl #5  ; <UNPREDICTABLE>
+0+184 <[^>]*> e151f113 ?       cmp     r1, r3, lsl r1  ; <UNPREDICTABLE>
+0+188 <[^>]*> e310f00a ?       tst     r0, #10 ; <UNPREDICTABLE>
+0+18c <[^>]*> e112f004 ?       tst     r2, r4  ; <UNPREDICTABLE>
+0+190 <[^>]*> e115f287 ?       tst     r5, r7, lsl #5  ; <UNPREDICTABLE>
+0+194 <[^>]*> e111f113 ?       tst     r1, r3, lsl r1  ; <UNPREDICTABLE>
 0+198 <[^>]*> e0000291 ?       mul     r0, r1, r2
 0+19c <[^>]*> e0110392 ?       muls    r1, r2, r3
 0+1a0 <[^>]*> 10000091 ?       mulne   r0, r1, r0

diff --git a/gas/testsuite/gas/arm/nops.d b/gas/testsuite/gas/arm/nops.d
new file mode 100644 (file)
index 0000000..0d57e66
--- /dev/null
+++ b/gas/testsuite/gas/arm/nops.d
@@ -0,0 +1,12 @@
+# name: NOP<c> instructions
+# objdump: -dr --prefix-addresses --show-raw-insn
+# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0+000 <[^>]*> 0320f000 ?       nopeq   \{0\}
+0+004 <[^>]*> 7320f000 ?       nopvc   \{0\}
+0+008 <[^>]*> 7320d700 ?       nopvc   \{0\}   ; <UNPREDICTABLE>
+
+

diff --git a/gas/testsuite/gas/arm/nops.s b/gas/testsuite/gas/arm/nops.s
new file mode 100644 (file)
index 0000000..704c10b
--- /dev/null
+++ b/gas/testsuite/gas/arm/nops.s
@@ -0,0 +1,4 @@
+.arm
+.inst 0x0320f000
+.inst 0x7320f000
+.inst 0x7320d700

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ac0b43314181137c28e3c0b942e0a4182bedff86..25892ea64c5cc9a2af14b9ea2f15094411d81a6d 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * arm-dis.c (print_insn_arm): Disassembling for all targets V6
+       and higher with ARM instruction set will now mark the 26-bit
+       versions of teq,tst,cmn and cmp as UNPREDICTABLE.
+       (arm_opcodes): Fix for unpredictable nop being recognized as a
+       teq.
+
 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 
        * micromips-opc.c (micromips_opcodes): Re-order table so that move

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 46bda78fe346329e5642c3e524a6d7e4821467e0..430da08863a6c0f48c1e938922cdb52ba74f08f8 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1647,6 +1647,8 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
+   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
+    0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
 
   /* ARM V6T2 instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -2124,11 +2126,13 @@ static const struct opcode32 arm_opcodes[] =
     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
 
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
-    0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
+    0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
-    0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
+    0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
-    0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
+    0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
+  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+    0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
 
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
@@ -2277,6 +2281,8 @@ static const struct opcode32 arm_opcodes[] =
     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
 
   /* The rest.  */
+  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
+    0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
   {ARM_FEATURE_CORE_LOW (0),
@@ -4655,6 +4661,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
                          if (! ARM_CPU_HAS_FEATURE (private_data->features, \
                                                     arm_ext_v6))
                            func (stream, "p");
+                         else
+                           is_unpredictable = TRUE;
                        }
                      break;