x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear

This combination makes no sense and is documented to cause #UD.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 0c99e5179b7cd55de92dd4b646a3e6deb7813c3a..02cef3c55932e80428a7afec78bf9f68c3a78ff6 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2021-03-25  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/i386/avx512f-nondef.s: Add case for EVEX.z
+       without mask register.
+       * testsuite/gas/i386/avx512f-nondef.d: Adjust expectations.
+
 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 
        * config/tc-i386.c (md_assemble): Widen set of insns to avoid

diff --git a/gas/testsuite/gas/i386/avx512f-nondef.d b/gas/testsuite/gas/i386/avx512f-nondef.d
index d768b7c27e452702805008c2dec75a0454df614f..6a9c5d375ac659a30ba2662826fd71d544b2e66c 100644 (file)
--- a/gas/testsuite/gas/i386/avx512f-nondef.d
+++ b/gas/testsuite/gas/i386/avx512f-nondef.d
@@ -1,6 +1,6 @@
 #as: 
 #objdump: -dw
-#name: i386 AVX512F insns with nondefault values in ignored bits
+#name: i386 AVX512F insns with nondefault values in ignored / reserved bits
 
 .*: +file format .*
 
@@ -16,4 +16,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    62                      vpmovdb %zmm6,\(bad\)
 [      ]*[a-f0-9]+:    f2 7e 58                bnd jle (0x7d|7d <.text\+0x7d>)
 [      ]*[a-f0-9]+:    31 72 7f                xor    %esi,0x7f\(%edx\)
+[      ]*[a-f0-9]+:    62 f1 7c 88 58          \(bad\)
+[      ]*[a-f0-9]+:    c3                      ret *
 #pass

diff --git a/gas/testsuite/gas/i386/avx512f-nondef.s b/gas/testsuite/gas/i386/avx512f-nondef.s
index 255d2c931f155fe88b579bb3c9979162dbeca180..b8b14fdf1450e30a49027a4a45d45a57bafeebe4 100644 (file)
--- a/gas/testsuite/gas/i386/avx512f-nondef.s
+++ b/gas/testsuite/gas/i386/avx512f-nondef.s
@@ -13,3 +13,5 @@
 .byte 0x62, 0xf2, 0x7e, 0x48, 0x31, 0x72, 0x7f
 # vpmovdb      %zmm6, 2032(%rdx) # with set EVEX.B bit - we should get (bad) operand
 .byte 0x62, 0xf2, 0x7e, 0x58, 0x31, 0x72, 0x7f
+# vaddps xmm0, xmm0, xmm3 # with EVEX.z set
+.byte 0x62, 0xf1, 0x7c, 0x88, 0x58, 0xc3

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bd02d2bfbfee8eda13ed91c3bbb59bdfbd20e0f1..a4c880b16dc1b190162ff2e1142aa14bea267576 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2021-03-25  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
+       zeroing-masking without masking.
+
 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 
        * i386-opc.tbl (invlpgb): Fix multi-operand form.

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 9e5c412fa4adaee94a1f9e19c748b467a138405e..00ed251eca7b8a3153c73bbd432229ff7912c7af 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -9739,6 +9739,13 @@ print_insn (bfd_vma pc, disassemble_info *info)
       return end_codep - priv.the_buffer;
     }
 
+  /* If EVEX.z is set, there must be an actual mask register in use.  */
+  if (vex.zeroing && vex.mask_register_specifier == 0)
+    {
+      (*info->fprintf_func) (info->stream, "(bad)");
+      return end_codep - priv.the_buffer;
+    }
+
   switch (dp->prefix_requirement)
     {
     case PREFIX_DATA: