ARM: meson: DTS: enable L2 cache

This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea5a711a788bedf28c128ada89b0185e1ed..862aae4a3285d7310ab77b4911dcbb031d4a8c3c 100644 (file)
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -50,6 +50,13 @@
 / {
        interrupt-parent = <&gic>;
 
+       L2: l2-cache-controller@c4200000 {
+               compatible = "arm,pl310-cache";
+               reg = <0xc4200000 0x1000>;
+               cache-unified;
+               cache-level = <2>;
+       };
+
        gic: interrupt-controller@c4301000 {
                compatible = "arm,cortex-a9-gic";
                reg = <0xc4301000 0x1000>,

diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 4ba49127779f04fe5147f0420560a74ebece70a2..8b33be15af943c81cad3dfd588077503da22c61f 100644 (file)
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -60,12 +60,14 @@
                cpu@200 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
                        reg = <0x200>;
                };
 
                cpu@201 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
                        reg = <0x201>;
                };
        };

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 42e4026c7ac1e4fe8b4a42330a09789396db2649..1f442a7fe03b758905205630ce3409105a88625a 100644 (file)
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -58,24 +58,28 @@
                cpu@200 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
                        reg = <0x200>;
                };
 
                cpu@201 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
                        reg = <0x201>;
                };
 
                cpu@202 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
                        reg = <0x202>;
                };
 
                cpu@203 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
                        reg = <0x203>;
                };
        };