* m10300-opc.c: SP-based offsets are always unsigned.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4e2200afaa72a9c2b8b720c19ce9c65d6155f10f..66a43ee4df74964085999c5571469e24bdbb429d 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2000-04-01  Alexandre Oliva  <aoliva@cygnus.com>
+
+       * m10300-opc.c: SP-based offsets are always unsigned.
+
 2000-03-29  Thomas de Lellis  <tdel@windriver.com>
 
        * arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"

diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c
index 9d90c5c4768f28990acb0c88502462966062862f..c779dbc1933dde5b60167e8b186cd645a8a11305 100644 (file)
--- a/opcodes/m10300-opc.c
+++ b/opcodes/m10300-opc.c
@@ -439,10 +439,10 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov",       0xfb8e0000,  0xffff000f,  0,    FMT_D7, AM33,   {MEM2(RI, RM0), RD2}},
 { "mov",       0xfb1a0000,  0xffff0000,  0,    FMT_D7, AM33,   {RM2, MEM2(SD8, RN0)}},
 { "mov",       0xfd1a0000,  0xffff0000,  0,    FMT_D8, AM33,   {RM2, MEM2(SD24, RN0)}},
-{ "mov",       0xfb8a0000,  0xffff0f00,  0,    FMT_D7, AM33,   {MEM2(SD8, SP), RN2}},
-{ "mov",       0xfd8a0000,  0xffff0f00,  0,    FMT_D8, AM33,   {MEM2(SD24, SP), RN2}},
-{ "mov",       0xfb9a0000,  0xffff0f00,  0,    FMT_D7, AM33,   {RM2, MEM2(SD8, SP)}},
-{ "mov",       0xfd9a0000,  0xffff0f00,  0,    FMT_D8, AM33,   {RM2, MEM2(SD24, SP)}},
+{ "mov",       0xfb8a0000,  0xffff0f00,  0,    FMT_D7, AM33,   {MEM2(IMM8, SP), RN2}},
+{ "mov",       0xfd8a0000,  0xffff0f00,  0,    FMT_D8, AM33,   {MEM2(IMM24, SP), RN2}},
+{ "mov",       0xfb9a0000,  0xffff0f00,  0,    FMT_D7, AM33,   {RM2, MEM2(IMM8, SP)}},
+{ "mov",       0xfd9a0000,  0xffff0f00,  0,    FMT_D8, AM33,   {RM2, MEM2(IMM24, SP)}},
 { "mov",       0xfb9e0000,  0xffff000f,  0,    FMT_D7, AM33,   {RD2, MEM2(RI, RN0)}},
 { "mov",       0xfb6a0000,  0xffff0000,  0x22, FMT_D7, AM33,   {MEMINC2 (RM0, SIMM8), RN2}},
 { "mov",       0xfb7a0000,  0xffff0000,  0,    FMT_D7, AM33,   {RM2, MEMINC2 (RN0, SIMM8)}},
@@ -574,10 +574,10 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "movbu",     0xfd2a0000,  0xffff0000,  0,    FMT_D8, AM33,   {MEM2(SD24, RM0), RN2}},
 { "movbu",     0xfb3a0000,  0xffff0000,  0,    FMT_D7, AM33,   {RM2, MEM2(SD8, RN0)}},
 { "movbu",     0xfd3a0000,  0xffff0000,  0,    FMT_D8, AM33,   {RM2, MEM2(SD24, RN0)}},
-{ "movbu",     0xfbaa0000,  0xffff0f00,  0,    FMT_D7, AM33,   {MEM2(SD8, SP), RN2}},
-{ "movbu",     0xfdaa0000,  0xffff0f00,  0,    FMT_D8, AM33,   {MEM2(SD24, SP), RN2}},
-{ "movbu",     0xfbba0000,  0xffff0f00,  0,    FMT_D7, AM33,   {RM2, MEM2(SD8, SP)}},
-{ "movbu",     0xfdba0000,  0xffff0f00,  0,    FMT_D8, AM33,   {RM2, MEM2(SD24, SP)}},
+{ "movbu",     0xfbaa0000,  0xffff0f00,  0,    FMT_D7, AM33,   {MEM2(IMM8, SP), RN2}},
+{ "movbu",     0xfdaa0000,  0xffff0f00,  0,    FMT_D8, AM33,   {MEM2(IMM24, SP), RN2}},
+{ "movbu",     0xfbba0000,  0xffff0f00,  0,    FMT_D7, AM33,   {RM2, MEM2(IMM8, SP)}},
+{ "movbu",     0xfdba0000,  0xffff0f00,  0,    FMT_D8, AM33,   {RM2, MEM2(IMM24, SP)}},
 { "movbu",     0xfb2e0000,  0xffff0f00,  0,    FMT_D7, AM33,   {MEM(IMM8_MEM), RN2}},
 { "movbu",     0xfd2e0000,  0xffff0f00,  0,    FMT_D8, AM33,   {MEM(IMM24_MEM), RN2}},
 { "movbu",     0xfb3e0000,  0xffff0f00,  0,    FMT_D7, AM33,   {RM2, MEM(IMM8_MEM)}},
@@ -623,10 +623,10 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "movhu",     0xfd4a0000,  0xffff0000,  0,    FMT_D8, AM33,   {MEM2(SD24, RM0), RN2}},
 { "movhu",     0xfb5a0000,  0xffff0000,  0,    FMT_D7, AM33,   {RM2, MEM2(SD8, RN0)}},
 { "movhu",     0xfd5a0000,  0xffff0000,  0,    FMT_D8, AM33,   {RM2, MEM2(SD24, RN0)}},
-{ "movhu",     0xfbca0000,  0xffff0f00,  0,    FMT_D7, AM33,   {MEM2(SD8, SP), RN2}},
-{ "movhu",     0xfdca0000,  0xffff0f00,  0,    FMT_D8, AM33,   {MEM2(SD24, SP), RN2}},
-{ "movhu",     0xfbda0000,  0xffff0f00,  0,    FMT_D7, AM33,   {RM2, MEM2(SD8, SP)}},
-{ "movhu",     0xfdda0000,  0xffff0f00,  0,    FMT_D8, AM33,   {RM2, MEM2(SD24, SP)}},
+{ "movhu",     0xfbca0000,  0xffff0f00,  0,    FMT_D7, AM33,   {MEM2(IMM8, SP), RN2}},
+{ "movhu",     0xfdca0000,  0xffff0f00,  0,    FMT_D8, AM33,   {MEM2(IMM24, SP), RN2}},
+{ "movhu",     0xfbda0000,  0xffff0f00,  0,    FMT_D7, AM33,   {RM2, MEM2(IMM8, SP)}},
+{ "movhu",     0xfdda0000,  0xffff0f00,  0,    FMT_D8, AM33,   {RM2, MEM2(IMM24, SP)}},
 { "movhu",     0xfb4e0000,  0xffff0f00,  0,    FMT_D7, AM33,   {MEM(IMM8_MEM), RN2}},
 { "movhu",     0xfd4e0000,  0xffff0f00,  0,    FMT_D8, AM33,   {MEM(IMM24_MEM), RN2}},
 { "movhu",     0xfbce0000,  0xffff000f,  0,    FMT_D7, AM33,   {MEM2(RI, RM0), RD2}},