powerpc/usb: remove checking PHY_CLK_VALID for UTMI PHY
authorShengzhou Liu <Shengzhou.Liu@freescale.com>
Mon, 24 Sep 2012 14:01:35 +0000 (22:01 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 24 Sep 2012 20:42:45 +0000 (13:42 -0700)
PHY_CLK_VALID bit doesn't work properly with UTMI PHY.
e.g. This bit is always zero on P5040, etc.
There is no need to check this bit for UTMI PHY, just keep
checking for ULPI PHY to prevent system hanging.

This patch should be squashed into previous commit 3735ba8db8e6e
"powerpc/usb: fix bug of CPU hang when missing USB PHY clock"

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/usb/host/ehci-fsl.c
include/linux/fsl_devices.h

index 11ff4b4dc7ad0e782ee9b8b0e02add9dd8aecb19..9bfde82078ecabde8236fc504aaf2a1794d25fb3 100644 (file)
@@ -267,8 +267,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
                break;
        }
 
-       if ((pdata->controller_ver) && ((phy_mode == FSL_USB2_PHY_ULPI) ||
-                       (phy_mode == FSL_USB2_PHY_UTMI))) {
+       if (pdata->controller_ver && (phy_mode == FSL_USB2_PHY_ULPI)) {
                /* check PHY_CLK_VALID to get phy clk valid */
                if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
                                PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
index 38b5660813ff25f219f1922071a73f21b5738289..a82296af413fbe981d2b6ff7a8453954d6a0e248 100644 (file)
@@ -19,7 +19,7 @@
 
 #define FSL_UTMI_PHY_DLY       10      /*As per P1010RM, delay for UTMI
                                PHY CLK to become stable - 10ms*/
-#define FSL_USB_PHY_CLK_TIMEOUT        1000    /* uSec */
+#define FSL_USB_PHY_CLK_TIMEOUT        10000   /* uSec */
 #define FSL_USB_VER_OLD                0
 #define FSL_USB_VER_1_6                1
 #define FSL_USB_VER_2_2                2
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