gas/

2007-06-25  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (process_operands): Replace regKludge
	with RegKludge.

opcodes/

2007-06-25  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (regKludge): Renamed to ...
	(RegKludge): This.

	* i386-opc.c (i386_optab): Replace regKludge with RegKludge.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 19a28fae3404a364001887794bdc5002b44a995a..cb45c263a62474bccd3ecaa699a3d490da3c5e13 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2007-06-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (process_operands): Replace regKludge
+       with RegKludge.
+
 2007-06-25  Richard Sandiford  <richard@codesourcery.com>
 
        * config/tc-mips.h (TC_SYMFIELD_TYPE): New.

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index ca868f985f301cc7f1fca65731ff1889f8d250f9..296fdcdde415d7ce1bdbf625a01370daa2676216 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3324,7 +3324,7 @@ process_operands (void)
   /* The imul $imm, %reg instruction is converted into
      imul $imm, %reg, %reg, and the clr %reg instruction
      is converted into xor %reg, %reg.  */
-  if (i.tm.opcode_modifier & regKludge)
+  if (i.tm.opcode_modifier & RegKludge)
     {
        if ((i.tm.cpu_flags & CpuSSE4_1))
         {

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e73bf0b6ea19b5f0b2be3cea14f8e3615614dc2b..ef72a2fe3bb8da2ec2f8c0ec810b4754c9c91185 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2007-06-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-opc.h (regKludge): Renamed to ...
+       (RegKludge): This.
+
+       * i386-opc.c (i386_optab): Replace regKludge with RegKludge.
+
 2007-06-23  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR binutils/4667

diff --git a/opcodes/i386-opc.c b/opcodes/i386-opc.c
index b0f48846f0e7b1ae175304a2e0712ef8fd53facd..b1d8cf45831e62b841db01939827e724e1d6ae8c 100644 (file)
--- a/opcodes/i386-opc.c
+++ b/opcodes/i386-opc.c
@@ -234,7 +234,7 @@ const template i386_optab[] =
 {"xor",           2,   0x80, 6, 0,      bwlq_Suf|W|Modrm,      { EncImm, Reg|AnyMem, 0} },
 
 /* clr with 1 operand is really xor with 2 operands.  */
-{"clr",           1,   0x30, X, 0,      bwlq_Suf|W|Modrm|regKludge,    { Reg, 0, 0 } },
+{"clr",           1,   0x30, X, 0,      bwlq_Suf|W|Modrm|RegKludge,    { Reg, 0, 0 } },
 
 {"adc",           2,   0x10, X, 0,      bwlq_Suf|D|W|Modrm,    { Reg, Reg|AnyMem, 0} },
 {"adc",           2,   0x83, 2, 0,      wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, 0} },
@@ -279,10 +279,10 @@ const template i386_optab[] =
 {"imul",   3,  0x6b, X, Cpu186, wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, WordReg} },
 {"imul",   3,  0x69, X, Cpu186, wlq_Suf|Modrm,         { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} },
 /* imul with 2 operands mimics imul with 3 by putting the register in
-   both i.rm.reg & i.rm.regmem fields.  regKludge enables this
+   both i.rm.reg & i.rm.regmem fields.  RegKludge enables this
    transformation.  */
-{"imul",   2,  0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
-{"imul",   2,  0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} },
+{"imul",   2,  0x6b, X, Cpu186, wlq_Suf|Modrm|RegKludge,{ Imm8S, WordReg, 0} },
+{"imul",   2,  0x69, X, Cpu186, wlq_Suf|Modrm|RegKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} },
 
 {"div",           1,   0xf6, 6, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 {"div",           2,   0xf6, 6, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, Acc, 0} },
@@ -1388,8 +1388,8 @@ const template i386_optab[] =
 
 {"blendpd",  3,  0x660f3a0d,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
 {"blendps",  3,  0x660f3a0c,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
-{"blendvpd", 3,  0x660f3815,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
-{"blendvps", 3,  0x660f3814,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"blendvpd", 3,  0x660f3815,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|RegKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"blendvps", 3,  0x660f3814,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|RegKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
 {"dppd",     3,  0x660f3a41,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
 {"dpps",     3,  0x660f3a40,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
 {"extractps",3,  0x660f3a17,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { Imm8, RegXMM, Reg32|Reg64|LongMem } },
@@ -1397,7 +1397,7 @@ const template i386_optab[] =
 {"movntdqa", 2,  0x660f382a,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { LLongMem, RegXMM, 0 } },
 {"mpsadbw",  3,  0x660f3a42,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
 {"packusdw", 2,  0x660f382b,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
-{"pblendvb", 3,  0x660f3810,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"pblendvb", 3,  0x660f3810,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|RegKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
 {"pblendw",  3,  0x660f3a0e,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
 {"pcmpeqq",  2,  0x660f3829,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
 {"pextrb",   3,  0x660f3a14,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,      { Imm8, RegXMM, Reg32|Reg64|ByteMem } },

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 019e5a828d17673763b987b73611959504dbbb30..5372d4a65aa886c43c13339ca0a0a97d2fd05629 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -116,7 +116,7 @@ typedef struct template
 #define No_xSuf       0x200000  /* x suffix on instruction illegal */
 #define FWait        0x400000  /* instruction needs FWAIT */
 #define IsString      0x800000 /* quick test for string instructions */
-#define regKludge    0x1000000 /* fake an extra reg operand for clr, imul
+#define RegKludge    0x1000000 /* fake an extra reg operand for clr, imul
                                   and special register processing for
                                   some instructions.  */
 #define IsPrefix     0x2000000 /* opcode is a prefix */