Merge branch 'v4.3-rc3-clk' of https://github.com/jamesjjliao/linux into clk-next

Pull mediatek clock support and fixes from James Liao:

"This is a collection of new Mediatek clocks support and fixes.
These patches come from Joe and me, including clock support for
subsystems, GPT and some minor fixes."

* 'v4.3-rc3-clk' of https://github.com/jamesjjliao/linux:
  clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS
  clk: mediatek: Add subsystem clocks of MT8173
  dt-bindings: ARM: Mediatek: Document devicetree bindings for clock controllers
  clk: mediatek: Fix rate and dependency of MT8173 clocks
  clk: mediatek: Add fixed clocks support for Mediatek SoC.
  clk: mediatek: Add __initdata and __init for data and functions
  clk: mediatek: Remove unused code from MT8173.
  clk: mediatek: Removed unused dpi_ck clock from MT8173
  clk: mediatek: add 13mhz clock for MT8173

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
new file mode 100644 (file)
index 0000000..b1f2ce1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
@@ -0,0 +1,22 @@
+Mediatek imgsys controller
+============================
+
+The Mediatek imgsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+       - "mediatek,mt8173-imgsys", "syscon"
+- #clock-cells: Must be 1
+
+The imgsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+imgsys: clock-controller@15000000 {
+       compatible = "mediatek,mt8173-imgsys", "syscon";
+       reg = <0 0x15000000 0 0x1000>;
+       #clock-cells = <1>;
+};

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
new file mode 100644 (file)
index 0000000..4385946
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -0,0 +1,22 @@
+Mediatek mmsys controller
+============================
+
+The Mediatek mmsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+       - "mediatek,mt8173-mmsys", "syscon"
+- #clock-cells: Must be 1
+
+The mmsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+mmsys: clock-controller@14000000 {
+       compatible = "mediatek,mt8173-mmsys", "syscon";
+       reg = <0 0x14000000 0 0x1000>;
+       #clock-cells = <1>;
+};

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
new file mode 100644 (file)
index 0000000..1faacf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -0,0 +1,22 @@
+Mediatek vdecsys controller
+============================
+
+The Mediatek vdecsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+       - "mediatek,mt8173-vdecsys", "syscon"
+- #clock-cells: Must be 1
+
+The vdecsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+vdecsys: clock-controller@16000000 {
+       compatible = "mediatek,mt8173-vdecsys", "syscon";
+       reg = <0 0x16000000 0 0x1000>;
+       #clock-cells = <1>;
+};

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencltsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencltsys.txt
new file mode 100644 (file)
index 0000000..3cc299f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencltsys.txt
@@ -0,0 +1,22 @@
+Mediatek vencltsys controller
+============================
+
+The Mediatek vencltsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+       - "mediatek,mt8173-vencltsys", "syscon"
+- #clock-cells: Must be 1
+
+The vencltsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+vencltsys: clock-controller@19000000 {
+       compatible = "mediatek,mt8173-vencltsys", "syscon";
+       reg = <0 0x19000000 0 0x1000>;
+       #clock-cells = <1>;
+};

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
new file mode 100644 (file)
index 0000000..5bb2866
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
@@ -0,0 +1,22 @@
+Mediatek vencsys controller
+============================
+
+The Mediatek vencsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+       - "mediatek,mt8173-vencsys", "syscon"
+- #clock-cells: Must be 1
+
+The vencsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+vencsys: clock-controller@18000000 {
+       compatible = "mediatek,mt8173-vencsys", "syscon";
+       reg = <0 0x18000000 0 0x1000>;
+       #clock-cells = <1>;
+};

diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 8e4b2a4635b96cb998951590dfb62d263c31b8e2..95fdfacb2ebf6828162c911da86a847804200599 100644 (file)
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,4 +1,4 @@
-obj-y += clk-mtk.o clk-pll.o clk-gate.o
+obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
 obj-y += clk-mt8135.o
 obj-y += clk-mt8173.o

diff --git a/drivers/clk/mediatek/clk-apmixed.c b/drivers/clk/mediatek/clk-apmixed.c
new file mode 100644 (file)
index 0000000..5303c59
--- /dev/null
+++ b/drivers/clk/mediatek/clk-apmixed.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+
+#define REF2USB_TX_EN          BIT(0)
+#define REF2USB_TX_LPF_EN      BIT(1)
+#define REF2USB_TX_OUT_EN      BIT(2)
+#define REF2USB_EN_MASK                (REF2USB_TX_EN | REF2USB_TX_LPF_EN | \
+                                REF2USB_TX_OUT_EN)
+
+struct mtk_ref2usb_tx {
+       struct clk_hw   hw;
+       void __iomem    *base_addr;
+};
+
+static inline struct mtk_ref2usb_tx *to_mtk_ref2usb_tx(struct clk_hw *hw)
+{
+       return container_of(hw, struct mtk_ref2usb_tx, hw);
+}
+
+static int mtk_ref2usb_tx_is_prepared(struct clk_hw *hw)
+{
+       struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
+
+       return (readl(tx->base_addr) & REF2USB_EN_MASK) == REF2USB_EN_MASK;
+}
+
+static int mtk_ref2usb_tx_prepare(struct clk_hw *hw)
+{
+       struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
+       u32 val;
+
+       val = readl(tx->base_addr);
+
+       val |= REF2USB_TX_EN;
+       writel(val, tx->base_addr);
+       udelay(100);
+
+       val |= REF2USB_TX_LPF_EN;
+       writel(val, tx->base_addr);
+
+       val |= REF2USB_TX_OUT_EN;
+       writel(val, tx->base_addr);
+
+       return 0;
+}
+
+static void mtk_ref2usb_tx_unprepare(struct clk_hw *hw)
+{
+       struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
+       u32 val;
+
+       val = readl(tx->base_addr);
+       val &= ~REF2USB_EN_MASK;
+       writel(val, tx->base_addr);
+}
+
+static const struct clk_ops mtk_ref2usb_tx_ops = {
+       .is_prepared    = mtk_ref2usb_tx_is_prepared,
+       .prepare        = mtk_ref2usb_tx_prepare,
+       .unprepare      = mtk_ref2usb_tx_unprepare,
+};
+
+struct clk * __init mtk_clk_register_ref2usb_tx(const char *name,
+                       const char *parent_name, void __iomem *reg)
+{
+       struct mtk_ref2usb_tx *tx;
+       struct clk_init_data init = {};
+       struct clk *clk;
+
+       tx = kzalloc(sizeof(*tx), GFP_KERNEL);
+       if (!tx)
+               return ERR_PTR(-ENOMEM);
+
+       tx->base_addr = reg;
+       tx->hw.init = &init;
+
+       init.name = name;
+       init.ops = &mtk_ref2usb_tx_ops;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+
+       clk = clk_register(NULL, &tx->hw);
+
+       if (IS_ERR(clk)) {
+               pr_err("Failed to register clk %s: %ld\n", name, PTR_ERR(clk));
+               kfree(tx);
+       }
+
+       return clk;
+}

diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 57020368a6934a490695fe174954c8485fdd2cc3..576bdb7c98b8c98f6ece22aea9ae80443ad2b887 100644 (file)
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -97,7 +97,7 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
        .disable        = mtk_cg_disable_inv,
 };
 
-struct clk *mtk_clk_register_gate(
+struct clk * __init mtk_clk_register_gate(
                const char *name,
                const char *parent_name,
                struct regmap *regmap,

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 90eff85f4285ec10415509ba8013b63d623f94cb..227e356403d9558346a6ef0b99b24eac50a3fd4f 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -15,21 +15,28 @@
 #include <linux/clk.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/slab.h>
-#include <linux/mfd/syscon.h>
 
 #include "clk-mtk.h"
 #include "clk-gate.h"
 
 #include <dt-bindings/clock/mt8173-clk.h>
 
+/*
+ * For some clocks, we don't care what their actual rates are. And these
+ * clocks may change their rate on different products or different scenarios.
+ * So we model these clocks' rate as 0, to denote it's not an actual rate.
+ */
+#define DUMMY_RATE             0
+
 static DEFINE_SPINLOCK(mt8173_clk_lock);
 
-static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
-       FACTOR(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk_null", 1, 1),
-       FACTOR(CLK_TOP_DPI, "dpi_ck", "clk_null", 1, 1),
-       FACTOR(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk_null", 1, 1),
-       FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "clk_null", 1, 1),
+static const struct mtk_fixed_clk fixed_clks[] __initconst = {
+       FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE),
+       FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
+       FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE),
+       FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE),
+       FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE),
+       FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE),
 };
 
 static const struct mtk_fixed_factor top_divs[] __initconst = {
@@ -54,6 +61,7 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
        FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
        FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
 
+       FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "tvdpll_445p5m", 1, 3),
        FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
        FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
 
@@ -590,7 +598,7 @@ static const struct mtk_composite top_muxes[] __initconst = {
        MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
 };
 
-static const struct mtk_gate_regs infra_cg_regs = {
+static const struct mtk_gate_regs infra_cg_regs __initconst = {
        .set_ofs = 0x0040,
        .clr_ofs = 0x0044,
        .sta_ofs = 0x0048,
@@ -612,20 +620,24 @@ static const struct mtk_gate infra_clks[] __initconst = {
        GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
        GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
        GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
-       GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "clk_null", 15),
+       GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
        GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
        GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
        GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
        GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
 };
 
-static const struct mtk_gate_regs peri0_cg_regs = {
+static const struct mtk_fixed_factor infra_divs[] __initconst = {
+       FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
+};
+
+static const struct mtk_gate_regs peri0_cg_regs __initconst = {
        .set_ofs = 0x0008,
        .clr_ofs = 0x0010,
        .sta_ofs = 0x0018,
 };
 
-static const struct mtk_gate_regs peri1_cg_regs = {
+static const struct mtk_gate_regs peri1_cg_regs __initconst = {
        .set_ofs = 0x000c,
        .clr_ofs = 0x0014,
        .sta_ofs = 0x001c,
@@ -701,6 +713,183 @@ static const struct mtk_composite peri_clks[] __initconst = {
        MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
 };
 
+static const struct mtk_gate_regs cg_regs_4_8_0 __initconst = {
+       .set_ofs = 0x0004,
+       .clr_ofs = 0x0008,
+       .sta_ofs = 0x0000,
+};
+
+#define GATE_IMG(_id, _name, _parent, _shift) {                        \
+               .id = _id,                                      \
+               .name = _name,                                  \
+               .parent_name = _parent,                         \
+               .regs = &cg_regs_4_8_0,                         \
+               .shift = _shift,                                \
+               .ops = &mtk_clk_gate_ops_setclr,                \
+       }
+
+static const struct mtk_gate img_clks[] __initconst = {
+       GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0),
+       GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5),
+       GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6),
+       GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7),
+       GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8),
+       GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9),
+       GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
+};
+
+static const struct mtk_gate_regs mm0_cg_regs __initconst = {
+       .set_ofs = 0x0104,
+       .clr_ofs = 0x0108,
+       .sta_ofs = 0x0100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs __initconst = {
+       .set_ofs = 0x0114,
+       .clr_ofs = 0x0118,
+       .sta_ofs = 0x0110,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) {                        \
+               .id = _id,                                      \
+               .name = _name,                                  \
+               .parent_name = _parent,                         \
+               .regs = &mm0_cg_regs,                           \
+               .shift = _shift,                                \
+               .ops = &mtk_clk_gate_ops_setclr,                \
+       }
+
+#define GATE_MM1(_id, _name, _parent, _shift) {                        \
+               .id = _id,                                      \
+               .name = _name,                                  \
+               .parent_name = _parent,                         \
+               .regs = &mm1_cg_regs,                           \
+               .shift = _shift,                                \
+               .ops = &mtk_clk_gate_ops_setclr,                \
+       }
+
+static const struct mtk_gate mm_clks[] __initconst = {
+       /* MM0 */
+       GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
+       GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
+       GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
+       GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
+       GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
+       GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
+       GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
+       GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
+       GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
+       GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
+       GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
+       GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
+       GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
+       GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
+       GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
+       GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
+       GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
+       GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
+       GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
+       GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
+       GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
+       GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
+       GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
+       GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
+       GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
+       GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
+       GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
+       GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
+       GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
+       GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
+       GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
+       /* MM1 */
+       GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
+       GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
+       GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
+       GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
+       GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
+       GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
+       GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
+       GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
+       GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
+       GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
+       GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
+       GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
+       GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
+       GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
+       GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
+       GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
+       GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
+       GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
+       GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
+       GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
+       GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
+};
+
+static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
+       .set_ofs = 0x0000,
+       .clr_ofs = 0x0004,
+       .sta_ofs = 0x0000,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs __initconst = {
+       .set_ofs = 0x0008,
+       .clr_ofs = 0x000c,
+       .sta_ofs = 0x0008,
+};
+
+#define GATE_VDEC0(_id, _name, _parent, _shift) {              \
+               .id = _id,                                      \
+               .name = _name,                                  \
+               .parent_name = _parent,                         \
+               .regs = &vdec0_cg_regs,                         \
+               .shift = _shift,                                \
+               .ops = &mtk_clk_gate_ops_setclr_inv,            \
+       }
+
+#define GATE_VDEC1(_id, _name, _parent, _shift) {              \
+               .id = _id,                                      \
+               .name = _name,                                  \
+               .parent_name = _parent,                         \
+               .regs = &vdec1_cg_regs,                         \
+               .shift = _shift,                                \
+               .ops = &mtk_clk_gate_ops_setclr_inv,            \
+       }
+
+static const struct mtk_gate vdec_clks[] __initconst = {
+       GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
+       GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0),
+};
+
+#define GATE_VENC(_id, _name, _parent, _shift) {               \
+               .id = _id,                                      \
+               .name = _name,                                  \
+               .parent_name = _parent,                         \
+               .regs = &cg_regs_4_8_0,                         \
+               .shift = _shift,                                \
+               .ops = &mtk_clk_gate_ops_setclr_inv,            \
+       }
+
+static const struct mtk_gate venc_clks[] __initconst = {
+       GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0),
+       GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4),
+       GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8),
+       GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12),
+};
+
+#define GATE_VENCLT(_id, _name, _parent, _shift) {             \
+               .id = _id,                                      \
+               .name = _name,                                  \
+               .parent_name = _parent,                         \
+               .regs = &cg_regs_4_8_0,                         \
+               .shift = _shift,                                \
+               .ops = &mtk_clk_gate_ops_setclr_inv,            \
+       }
+
+static const struct mtk_gate venclt_clks[] __initconst = {
+       GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0),
+       GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
+};
+
 static struct clk_onecell_data *mt8173_top_clk_data __initdata;
 static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
 
@@ -731,7 +920,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
 
        mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
 
-       mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
+       mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data);
        mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
        mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
                        &mt8173_clk_lock, clk_data);
@@ -754,6 +943,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 
        mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
                                                clk_data);
+       mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
 
        r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
        if (r)
@@ -792,6 +982,24 @@ static void __init mtk_pericfg_init(struct device_node *node)
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
+struct mtk_clk_usb {
+       int id;
+       const char *name;
+       const char *parent;
+       u32 reg_ofs;
+};
+
+#define APMIXED_USB(_id, _name, _parent, _reg_ofs) {                   \
+               .id = _id,                                              \
+               .name = _name,                                          \
+               .parent = _parent,                                      \
+               .reg_ofs = _reg_ofs,                                    \
+       }
+
+static const struct mtk_clk_usb apmixed_usb[] __initconst = {
+       APMIXED_USB(CLK_APMIXED_REF2USB_TX, "ref2usb_tx", "clk26m", 0x8),
+};
+
 #define MT8173_PLL_FMAX                (3000UL * MHZ)
 
 #define CON0_MT8173_RST_BAR    BIT(24)
@@ -852,6 +1060,15 @@ static const struct mtk_pll_data plls[] = {
 static void __init mtk_apmixedsys_init(struct device_node *node)
 {
        struct clk_onecell_data *clk_data;
+       void __iomem *base;
+       struct clk *clk;
+       int r, i;
+
+       base = of_iomap(node, 0);
+       if (!base) {
+               pr_err("%s(): ioremap failed\n", __func__);
+               return;
+       }
 
        mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
        if (!clk_data)
@@ -859,7 +1076,113 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
 
        mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
 
+       for (i = 0; i < ARRAY_SIZE(apmixed_usb); i++) {
+               const struct mtk_clk_usb *cku = &apmixed_usb[i];
+
+               clk = mtk_clk_register_ref2usb_tx(cku->name, cku->parent,
+                                       base + cku->reg_ofs);
+
+               if (IS_ERR(clk)) {
+                       pr_err("Failed to register clk %s: %ld\n", cku->name,
+                                       PTR_ERR(clk));
+                       continue;
+               }
+
+               clk_data->clks[cku->id] = clk;
+       }
+
+       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+       if (r)
+               pr_err("%s(): could not register clock provider: %d\n",
+                       __func__, r);
+
        mtk_clk_enable_critical();
 }
 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
                mtk_apmixedsys_init);
+
+static void __init mtk_imgsys_init(struct device_node *node)
+{
+       struct clk_onecell_data *clk_data;
+       int r;
+
+       clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
+
+       mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
+                                               clk_data);
+
+       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+       if (r)
+               pr_err("%s(): could not register clock provider: %d\n",
+                       __func__, r);
+}
+CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
+
+static void __init mtk_mmsys_init(struct device_node *node)
+{
+       struct clk_onecell_data *clk_data;
+       int r;
+
+       clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+
+       mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+                                               clk_data);
+
+       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+       if (r)
+               pr_err("%s(): could not register clock provider: %d\n",
+                       __func__, r);
+}
+CLK_OF_DECLARE(mtk_mmsys, "mediatek,mt8173-mmsys", mtk_mmsys_init);
+
+static void __init mtk_vdecsys_init(struct device_node *node)
+{
+       struct clk_onecell_data *clk_data;
+       int r;
+
+       clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
+
+       mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
+                                               clk_data);
+
+       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+       if (r)
+               pr_err("%s(): could not register clock provider: %d\n",
+                       __func__, r);
+}
+CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init);
+
+static void __init mtk_vencsys_init(struct device_node *node)
+{
+       struct clk_onecell_data *clk_data;
+       int r;
+
+       clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
+
+       mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
+                                               clk_data);
+
+       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+       if (r)
+               pr_err("%s(): could not register clock provider: %d\n",
+                       __func__, r);
+}
+CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init);
+
+static void __init mtk_vencltsys_init(struct device_node *node)
+{
+       struct clk_onecell_data *clk_data;
+       int r;
+
+       clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK);
+
+       mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks),
+                                               clk_data);
+
+       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+       if (r)
+               pr_err("%s(): could not register clock provider: %d\n",
+                       __func__, r);
+}
+CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_init);

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 18444aea63c93c1eb491d3a574fe351895768374..cf08db6c130c9887e6bc4ed40415aa683efd9b8d 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -24,7 +24,7 @@
 #include "clk-mtk.h"
 #include "clk-gate.h"
 
-struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
+struct clk_onecell_data * __init mtk_alloc_clk_data(unsigned int clk_num)
 {
        int i;
        struct clk_onecell_data *clk_data;
@@ -49,8 +49,31 @@ err_out:
        return NULL;
 }
 
-void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
-               struct clk_onecell_data *clk_data)
+void __init mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
+               int num, struct clk_onecell_data *clk_data)
+{
+       int i;
+       struct clk *clk;
+
+       for (i = 0; i < num; i++) {
+               const struct mtk_fixed_clk *rc = &clks[i];
+
+               clk = clk_register_fixed_rate(NULL, rc->name, rc->parent,
+                               rc->parent ? 0 : CLK_IS_ROOT, rc->rate);
+
+               if (IS_ERR(clk)) {
+                       pr_err("Failed to register clk %s: %ld\n",
+                                       rc->name, PTR_ERR(clk));
+                       continue;
+               }
+
+               if (clk_data)
+                       clk_data->clks[rc->id] = clk;
+       }
+}
+
+void __init mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
+               int num, struct clk_onecell_data *clk_data)
 {
        int i;
        struct clk *clk;
@@ -72,7 +95,8 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
        }
 }
 
-int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
+int __init mtk_clk_register_gates(struct device_node *node,
+               const struct mtk_gate *clks,
                int num, struct clk_onecell_data *clk_data)
 {
        int i;
@@ -111,7 +135,7 @@ int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks
        return 0;
 }
 
-struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
+struct clk * __init mtk_clk_register_composite(const struct mtk_composite *mc,
                void __iomem *base, spinlock_t *lock)
 {
        struct clk *clk;
@@ -196,7 +220,7 @@ err_out:
        return ERR_PTR(ret);
 }
 
-void mtk_clk_register_composites(const struct mtk_composite *mcs,
+void __init mtk_clk_register_composites(const struct mtk_composite *mcs,
                int num, void __iomem *base, spinlock_t *lock,
                struct clk_onecell_data *clk_data)
 {

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c5cbecb3d218c3d33e116db2d814819987067e8d..32d2e455eb3fbd0bb3e59434af25d4c0d26f0158 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -26,6 +26,23 @@ struct clk;
 
 #define MHZ (1000 * 1000)
 
+struct mtk_fixed_clk {
+       int id;
+       const char *name;
+       const char *parent;
+       unsigned long rate;
+};
+
+#define FIXED_CLK(_id, _name, _parent, _rate) {                \
+               .id = _id,                              \
+               .name = _name,                          \
+               .parent = _parent,                      \
+               .rate = _rate,                          \
+       }
+
+void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
+               int num, struct clk_onecell_data *clk_data);
+
 struct mtk_fixed_factor {
        int id;
        const char *name;
@@ -42,7 +59,7 @@ struct mtk_fixed_factor {
                .div = _div,                            \
        }
 
-extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
+void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
                int num, struct clk_onecell_data *clk_data);
 
 struct mtk_composite {
@@ -159,10 +176,13 @@ struct mtk_pll_data {
        const struct mtk_pll_div_table *div_table;
 };
 
-void __init mtk_clk_register_plls(struct device_node *node,
+void mtk_clk_register_plls(struct device_node *node,
                const struct mtk_pll_data *plls, int num_plls,
                struct clk_onecell_data *clk_data);
 
+struct clk *mtk_clk_register_ref2usb_tx(const char *name,
+                       const char *parent_name, void __iomem *reg);
+
 #ifdef CONFIG_RESET_CONTROLLER
 void mtk_register_reset_controller(struct device_node *np,
                        unsigned int num_regs, int regofs);

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 622e7b6c62b42893f1c4c98574a492eed361130e..966cab1348dad869f0de40b3699a770ec17ffe35 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -317,7 +317,7 @@ void __init mtk_clk_register_plls(struct device_node *node,
                const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
 {
        void __iomem *base;
-       int r, i;
+       int i;
        struct clk *clk;
 
        base = of_iomap(node, 0);
@@ -339,9 +339,4 @@ void __init mtk_clk_register_plls(struct device_node *node,
 
                clk_data->clks[pll->id] = clk;
        }
-
-       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-       if (r)
-               pr_err("%s(): could not register clock provider: %d\n",
-                       __func__, r);
 }

diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
index 4ad76ed882ad3abd9c61dc730a66a9c6753262a1..7956ba1bc9744a5fccd7b5b3cc915929752a146f 100644 (file)
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -18,7 +18,6 @@
 /* TOPCKGEN */
 
 #define CLK_TOP_CLKPH_MCK_O            1
-#define CLK_TOP_DPI                    2
 #define CLK_TOP_USB_SYSPLL_125M                3
 #define CLK_TOP_HDMITX_DIG_CTS         4
 #define CLK_TOP_ARMCA7PLL_754M         5
@@ -154,12 +153,16 @@
 #define CLK_TOP_I2S2_M_SEL             135
 #define CLK_TOP_I2S3_M_SEL             136
 #define CLK_TOP_I2S3_B_SEL             137
-#define CLK_TOP_NR_CLK                 138
+#define CLK_TOP_DSI0_DIG               138
+#define CLK_TOP_DSI1_DIG               139
+#define CLK_TOP_LVDS_PXL               140
+#define CLK_TOP_LVDS_CTS               141
+#define CLK_TOP_NR_CLK                 142
 
 /* APMIXED_SYS */
 
-#define CLK_APMIXED_ARMCA15PLL 1
-#define CLK_APMIXED_ARMCA7PLL  2
+#define CLK_APMIXED_ARMCA15PLL         1
+#define CLK_APMIXED_ARMCA7PLL          2
 #define CLK_APMIXED_MAINPLL            3
 #define CLK_APMIXED_UNIVPLL            4
 #define CLK_APMIXED_MMPLL              5
@@ -172,7 +175,8 @@
 #define CLK_APMIXED_APLL2              12
 #define CLK_APMIXED_LVDSPLL            13
 #define CLK_APMIXED_MSDCPLL2           14
-#define CLK_APMIXED_NR_CLK             15
+#define CLK_APMIXED_REF2USB_TX         15
+#define CLK_APMIXED_NR_CLK             16
 
 /* INFRA_SYS */
 
@@ -187,7 +191,8 @@
 #define CLK_INFRA_CEC                  9
 #define CLK_INFRA_PMICSPI              10
 #define CLK_INFRA_PMICWRAP             11
-#define CLK_INFRA_NR_CLK               12
+#define CLK_INFRA_CLK_13M              12
+#define CLK_INFRA_NR_CLK               13
 
 /* PERI_SYS */
 
@@ -232,4 +237,91 @@
 #define CLK_PERI_UART3_SEL             39
 #define CLK_PERI_NR_CLK                        40
 
+/* IMG_SYS */
+
+#define CLK_IMG_LARB2_SMI              1
+#define CLK_IMG_CAM_SMI                        2
+#define CLK_IMG_CAM_CAM                        3
+#define CLK_IMG_SEN_TG                 4
+#define CLK_IMG_SEN_CAM                        5
+#define CLK_IMG_CAM_SV                 6
+#define CLK_IMG_FD                     7
+#define CLK_IMG_NR_CLK                 8
+
+/* MM_SYS */
+
+#define CLK_MM_SMI_COMMON              1
+#define CLK_MM_SMI_LARB0               2
+#define CLK_MM_CAM_MDP                 3
+#define CLK_MM_MDP_RDMA0               4
+#define CLK_MM_MDP_RDMA1               5
+#define CLK_MM_MDP_RSZ0                        6
+#define CLK_MM_MDP_RSZ1                        7
+#define CLK_MM_MDP_RSZ2                        8
+#define CLK_MM_MDP_TDSHP0              9
+#define CLK_MM_MDP_TDSHP1              10
+#define CLK_MM_MDP_WDMA                        11
+#define CLK_MM_MDP_WROT0               12
+#define CLK_MM_MDP_WROT1               13
+#define CLK_MM_FAKE_ENG                        14
+#define CLK_MM_MUTEX_32K               15
+#define CLK_MM_DISP_OVL0               16
+#define CLK_MM_DISP_OVL1               17
+#define CLK_MM_DISP_RDMA0              18
+#define CLK_MM_DISP_RDMA1              19
+#define CLK_MM_DISP_RDMA2              20
+#define CLK_MM_DISP_WDMA0              21
+#define CLK_MM_DISP_WDMA1              22
+#define CLK_MM_DISP_COLOR0             23
+#define CLK_MM_DISP_COLOR1             24
+#define CLK_MM_DISP_AAL                        25
+#define CLK_MM_DISP_GAMMA              26
+#define CLK_MM_DISP_UFOE               27
+#define CLK_MM_DISP_SPLIT0             28
+#define CLK_MM_DISP_SPLIT1             29
+#define CLK_MM_DISP_MERGE              30
+#define CLK_MM_DISP_OD                 31
+#define CLK_MM_DISP_PWM0MM             32
+#define CLK_MM_DISP_PWM026M            33
+#define CLK_MM_DISP_PWM1MM             34
+#define CLK_MM_DISP_PWM126M            35
+#define CLK_MM_DSI0_ENGINE             36
+#define CLK_MM_DSI0_DIGITAL            37
+#define CLK_MM_DSI1_ENGINE             38
+#define CLK_MM_DSI1_DIGITAL            39
+#define CLK_MM_DPI_PIXEL               40
+#define CLK_MM_DPI_ENGINE              41
+#define CLK_MM_DPI1_PIXEL              42
+#define CLK_MM_DPI1_ENGINE             43
+#define CLK_MM_HDMI_PIXEL              44
+#define CLK_MM_HDMI_PLLCK              45
+#define CLK_MM_HDMI_AUDIO              46
+#define CLK_MM_HDMI_SPDIF              47
+#define CLK_MM_LVDS_PIXEL              48
+#define CLK_MM_LVDS_CTS                        49
+#define CLK_MM_SMI_LARB4               50
+#define CLK_MM_HDMI_HDCP               51
+#define CLK_MM_HDMI_HDCP24M            52
+#define CLK_MM_NR_CLK                  53
+
+/* VDEC_SYS */
+
+#define CLK_VDEC_CKEN                  1
+#define CLK_VDEC_LARB_CKEN             2
+#define CLK_VDEC_NR_CLK                        3
+
+/* VENC_SYS */
+
+#define CLK_VENC_CKE0                  1
+#define CLK_VENC_CKE1                  2
+#define CLK_VENC_CKE2                  3
+#define CLK_VENC_CKE3                  4
+#define CLK_VENC_NR_CLK                        5
+
+/* VENCLT_SYS */
+
+#define CLK_VENCLT_CKE0                        1
+#define CLK_VENCLT_CKE1                        2
+#define CLK_VENCLT_NR_CLK              3
+
 #endif /* _DT_BINDINGS_CLK_MT8173_H */