ARM: KVM: fix vgic V7 assembler code to work in BE image

The vgic h/w registers are little endian; when BE asm code
reads/writes from/to them, it needs to do byteswap after/before.
Byteswap code uses ARM_BE8 wrapper to add swap only if
CONFIG_CPU_BIG_ENDIAN is configured.

Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index e4eaf30205c5c93a41104f9549f5537411750470..68d99c69639cab32331ceb7dc37e5016a38d0913 100644 (file)
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -1,4 +1,5 @@
 #include <linux/irqchip/arm-gic.h>
+#include <asm/assembler.h>
 
 #define VCPU_USR_REG(_reg_nr)  (VCPU_USR_REGS + (_reg_nr * 4))
 #define VCPU_USR_SP            (VCPU_USR_REG(13))
@@ -420,6 +421,14 @@ vcpu       .req    r0              @ vcpu pointer always in r0
        ldr     r8, [r2, #GICH_ELRSR0]
        ldr     r9, [r2, #GICH_ELRSR1]
        ldr     r10, [r2, #GICH_APR]
+ARM_BE8(rev    r3, r3  )
+ARM_BE8(rev    r4, r4  )
+ARM_BE8(rev    r5, r5  )
+ARM_BE8(rev    r6, r6  )
+ARM_BE8(rev    r7, r7  )
+ARM_BE8(rev    r8, r8  )
+ARM_BE8(rev    r9, r9  )
+ARM_BE8(rev    r10, r10        )
 
        str     r3, [r11, #VGIC_V2_CPU_HCR]
        str     r4, [r11, #VGIC_V2_CPU_VMCR]
@@ -439,6 +448,7 @@ vcpu        .req    r0              @ vcpu pointer always in r0
        add     r3, r11, #VGIC_V2_CPU_LR
        ldr     r4, [r11, #VGIC_CPU_NR_LR]
 1:     ldr     r6, [r2], #4
+ARM_BE8(rev    r6, r6  )
        str     r6, [r3], #4
        subs    r4, r4, #1
        bne     1b
@@ -466,6 +476,9 @@ vcpu        .req    r0              @ vcpu pointer always in r0
        ldr     r3, [r11, #VGIC_V2_CPU_HCR]
        ldr     r4, [r11, #VGIC_V2_CPU_VMCR]
        ldr     r8, [r11, #VGIC_V2_CPU_APR]
+ARM_BE8(rev    r3, r3  )
+ARM_BE8(rev    r4, r4  )
+ARM_BE8(rev    r8, r8  )
 
        str     r3, [r2, #GICH_HCR]
        str     r4, [r2, #GICH_VMCR]
@@ -476,6 +489,7 @@ vcpu        .req    r0              @ vcpu pointer always in r0
        add     r3, r11, #VGIC_V2_CPU_LR
        ldr     r4, [r11, #VGIC_CPU_NR_LR]
 1:     ldr     r6, [r3], #4
+ARM_BE8(rev    r6, r6  )
        str     r6, [r2], #4
        subs    r4, r4, #1
        bne     1b