# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
- common.o gpio.o dma.o wd_timer.o display.o i2c.o
+ common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
omap-2-3-common = irq.o sdrc.o
hwmod-common = omap_hwmod.o \
powerdomains44xx_data.o
# PRCM clockdomain control
-obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
+clockdomain-common += clockdomain.o \
+ clockdomains_common_data.o
+obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) \
clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
+obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) \
clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o \
clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
+obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) \
clockdomain44xx.o \
clockdomains44xx_data.o
obj-y += dsp.o
endif
+# OMAP2420 MSDI controller integration support ("MMC")
+obj-$(CONFIG_SOC_OMAP2420) += msdi.o
+
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
clk->ops->disable(clk);
}
if (clk->clkdm != NULL)
- pwrdm_clkdm_state_switch(clk->clkdm);
+ pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
}
#endif
/*
* OMAP3 clock data
*
- * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Written by Paul Walmsley
.name = "hdq_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &core_12m_fck,
+ .clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.recalc = &followparent_recalc,
CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
- CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX),
- CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX),
+ CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
- CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517),
+ CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
struct omap_clk *c;
u32 cpu_clkflg = 0;
- /*
- * 3505 must be tested before 3517, since 3517 returns true
- * for both AM3517 chips and AM3517 family chips, which
- * includes 3505. Unfortunately there's no obvious family
- * test for 3517/3505 :-(
- */
- if (cpu_is_omap3505()) {
- cpu_mask = RATE_IN_34XX;
- cpu_clkflg = CK_3505;
- } else if (cpu_is_omap3517()) {
- cpu_mask = RATE_IN_34XX;
- cpu_clkflg = CK_3517;
- } else if (cpu_is_omap3505()) {
+ if (cpu_is_omap3517()) {
cpu_mask = RATE_IN_34XX;
- cpu_clkflg = CK_3505;
+ cpu_clkflg = CK_AM35XX;
} else if (cpu_is_omap3630()) {
cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
cpu_clkflg = CK_36XX;
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
- CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
- CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
- CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
- CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
- CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
- CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
- CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
- CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
- CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
- CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
- CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
spin_lock_irqsave(&clkdm->lock, flags);
clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
arch_clkdm->clkdm_allow_idle(clkdm);
- pwrdm_clkdm_state_switch(clkdm);
+ pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
}
spin_lock_irqsave(&clkdm->lock, flags);
arch_clkdm->clkdm_clk_enable(clkdm);
- pwrdm_wait_transition(clkdm->pwrdm.ptr);
- pwrdm_clkdm_state_switch(clkdm);
+ pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
spin_lock_irqsave(&clkdm->lock, flags);
arch_clkdm->clkdm_clk_disable(clkdm);
- pwrdm_clkdm_state_switch(clkdm);
+ pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
struct clkdm_dep *cd;
u32 mask = 0;
+ if (!clkdm->prcm_partition)
+ return 0;
+
for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
if (!cd->clkdm)
continue; /* only happens if data is erroneous */
{
bool hwsup = false;
+ if (!clkdm->prcm_partition)
+ return 0;
+
hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);
.pwrdm = { .name = "wkup_pwrdm" },
.dep_bit = OMAP_EN_WKUP_SHIFT,
};
-
-struct clockdomain prm_common_clkdm = {
- .name = "prm_clkdm",
- .pwrdm = { .name = "wkup_pwrdm" },
-};
-
-struct clockdomain cm_common_clkdm = {
- .name = "cm_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
-};
* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
*/
static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
- { .clkdm_name = "iva2_clkdm", },
- { .clkdm_name = "mpu_clkdm", },
- { .clkdm_name = "wkup_clkdm", },
+ { .clkdm_name = "iva2_clkdm" },
+ { .clkdm_name = "mpu_clkdm" },
+ { .clkdm_name = "wkup_clkdm" },
{ NULL },
};
&l4_wkup_44xx_clkdm,
&emu_sys_44xx_clkdm,
&l3_dma_44xx_clkdm,
+ &prm_common_clkdm,
+ &cm_common_clkdm,
NULL
};
--- /dev/null
+/*
+ * OMAP2+-common clockdomain data
+ *
+ * Copyright (C) 2008-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+
+/* These are implicit clockdomains - they are never defined as such in TRM */
+struct clockdomain prm_common_clkdm = {
+ .name = "prm_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+};
+
+struct clockdomain cm_common_clkdm = {
+ .name = "cm_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+};
/* CM_CLKSEL1_PLL_IVA2 */
#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
-#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
+#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)
#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
/* CM_CLKSEL1_PLL_MPU */
#define OMAP3430_MPU_CLK_SRC_SHIFT 19
-#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
+#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)
#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
#include "prcm44xx.h"
#include "prm44xx.h"
#include "prcm_mpu44xx.h"
+#include "prcm-common.h"
/*
* CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
#define CLKCTRL_IDLEST_DISABLED 0x3
-static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
- [OMAP4430_INVALID_PRCM_PARTITION] = 0,
- [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE,
- [OMAP4430_CM1_PARTITION] = OMAP4430_CM1_BASE,
- [OMAP4430_CM2_PARTITION] = OMAP4430_CM2_BASE,
- [OMAP4430_SCRM_PARTITION] = 0,
- [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE,
-};
+static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
+
+/**
+ * omap_cm_base_init - Populates the cm partitions
+ *
+ * Populates the base addresses of the _cm_bases
+ * array used for read/write of cm module registers.
+ */
+void omap_cm_base_init(void)
+{
+ _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
+ _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
+ _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
+ _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+}
/* Private functions */
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]);
- return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+ return __raw_readl(_cm_bases[part] + inst + idx);
}
/* Write into a register in a CM instance */
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]);
- __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+ __raw_writel(val, _cm_bases[part] + inst + idx);
}
/* Read-modify-write a register in CM1. Caller must lock */
.prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
.cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
.cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
+ .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
};
void __init omap2_set_globals_443x(void)
void __iomem *prm; /* Power and Reset Management */
void __iomem *cm; /* Clock Management */
void __iomem *cm2;
+ void __iomem *prcm_mpu;
};
void omap2_set_globals_242x(void);
ai = omap3_dpll_autoidle_read(clk);
- omap3_dpll_deny_idle(clk);
+ if (ai)
+ omap3_dpll_deny_idle(clk);
_omap3_dpll_write_clken(clk, DPLL_LOCKED);
if (ai)
omap3_dpll_allow_idle(clk);
- else
- omap3_dpll_deny_idle(clk);
return r;
}
if (ai)
omap3_dpll_allow_idle(clk);
- else
- omap3_dpll_deny_idle(clk);
return 0;
}
dd = clk->dpll_data;
+ if (!dd->autoidle_reg)
+ return -EINVAL;
+
v = __raw_readl(dd->autoidle_reg);
v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask);
dd = clk->dpll_data;
+ if (!dd->autoidle_reg) {
+ pr_debug("clock: DPLL %s: autoidle not supported\n",
+ clk->name);
+ return;
+ }
+
/*
* REVISIT: CORE DPLL can optionally enter low-power bypass
* by writing 0x5 instead of 0x1. Add some mechanism to
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
__raw_writel(v, dd->autoidle_reg);
+
}
/**
dd = clk->dpll_data;
+ if (!dd->autoidle_reg) {
+ pr_debug("clock: DPLL %s: autoidle not supported\n",
+ clk->name);
+ return;
+ }
+
v = __raw_readl(dd->autoidle_reg);
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
--- /dev/null
+/*
+ * IP block integration code for the HDQ1W/1-wire IP block
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
+ * Avinash.H.M <avinashhm@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#include <plat/omap_hwmod.h>
+#include <plat/hdq1w.h>
+
+#include "common.h"
+
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT 10000
+
+/**
+ * omap_hdq1w_reset - reset the OMAP HDQ1W module
+ * @oh: struct omap_hwmod *
+ *
+ * OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire
+ * Software Reset" of the OMAP34xx Technical Reference Manual Revision
+ * ZR (SWPU223R) does not include the rather important fact that, for
+ * the reset to succeed, the HDQ1W module's internal clock gate must be
+ * programmed to allow the clock to propagate to the rest of the
+ * module. In this sense, it's rather similar to the I2C custom reset
+ * function. Returns 0.
+ */
+int omap_hdq1w_reset(struct omap_hwmod *oh)
+{
+ u32 v;
+ int c = 0;
+
+ /* Write to the SOFTRESET bit */
+ omap_hwmod_softreset(oh);
+
+ /* Enable the module's internal clocks */
+ v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
+ v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
+ omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
+
+ /* Poll on RESETDONE bit */
+ omap_test_timeout((omap_hwmod_read(oh,
+ oh->class->sysc->syss_offs)
+ & SYSS_RESETDONE_MASK),
+ MAX_MODULE_SOFTRESET_WAIT, c);
+
+ if (c == MAX_MODULE_SOFTRESET_WAIT)
+ pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+ __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+ else
+ pr_debug("%s: %s: softreset in %d usec\n", __func__,
+ oh->name, c);
+
+ return 0;
+}
#endif
omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
- /*
- * Set the default postsetup state for unusual modules (like
- * MPU WDT).
- *
- * The postsetup_state is not actually used until
- * omap_hwmod_late_init(), so boards that desire full watchdog
- * coverage of kernel initialization can reprogram the
- * postsetup_state between the calls to
- * omap2_init_common_infra() and omap_sdrc_init().
- *
- * XXX ideally we could detect whether the MPU WDT was currently
- * enabled here and make this conditional
- */
- postsetup_state = _HWMOD_STATE_DISABLED;
- omap_hwmod_for_each_by_class("wd_timer",
- _set_hwmod_postsetup_state,
- &postsetup_state);
-
omap_pm_if_early_init();
}
--- /dev/null
+/*
+ * MSDI IP block reset
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * XXX What about pad muxing?
+ */
+
+#include <linux/kernel.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/mmc.h>
+
+#include "common.h"
+
+/*
+ * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
+ * from the IP block's base address
+ */
+#define MSDI_CON_OFFSET 0x0c
+
+/* Register bitfields in the CON register */
+#define MSDI_CON_POW_MASK BIT(11)
+#define MSDI_CON_CLKD_MASK (0x3f << 0)
+#define MSDI_CON_CLKD_SHIFT 0
+
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT 10000
+
+/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
+#define MSDI_TARGET_RESET_CLKD 0x3ff
+
+/**
+ * omap_msdi_reset - reset the MSDI IP block
+ * @oh: struct omap_hwmod *
+ *
+ * The MSDI IP block on OMAP2420 has to have both the POW and CLKD
+ * fields set inside its CON register for a reset to complete
+ * successfully. This is not documented in the TRM. For CLKD, we use
+ * the value that results in the lowest possible clock rate, to attempt
+ * to avoid disturbing any cards.
+ */
+int omap_msdi_reset(struct omap_hwmod *oh)
+{
+ u16 v = 0;
+ int c = 0;
+
+ /* Write to the SOFTRESET bit */
+ omap_hwmod_softreset(oh);
+
+ /* Enable the MSDI core and internal clock */
+ v |= MSDI_CON_POW_MASK;
+ v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
+ omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
+
+ /* Poll on RESETDONE bit */
+ omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
+ & SYSS_RESETDONE_MASK),
+ MAX_MODULE_SOFTRESET_WAIT, c);
+
+ if (c == MAX_MODULE_SOFTRESET_WAIT)
+ pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+ __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+ else
+ pr_debug("%s: %s: softreset in %d usec\n", __func__,
+ oh->name, c);
+
+ /* Disable the MSDI internal clock */
+ v &= ~MSDI_CON_CLKD_MASK;
+ omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
+
+ return 0;
+}
* omap_hwmod implementation for OMAP2/3/4
*
* Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011-2012 Texas Instruments, Inc.
*
* Paul Walmsley, Benoît Cousson, Kevin Hilman
*
#include <linux/mutex.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
+#include <linux/bootmem.h>
#include "common.h"
#include <plat/cpu.h>
/* Name of the OMAP hwmod for the MPU */
#define MPU_INITIATOR_NAME "mpu"
+/*
+ * Number of struct omap_hwmod_link records per struct
+ * omap_hwmod_ocp_if record (master->slave and slave->master)
+ */
+#define LINKS_PER_OCP_IF 2
+
/* omap_hwmod_list contains all registered struct omap_hwmods */
static LIST_HEAD(omap_hwmod_list);
/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
static struct omap_hwmod *mpu_oh;
+/*
+ * linkspace: ptr to a buffer that struct omap_hwmod_link records are
+ * allocated from - used to reduce the number of small memory
+ * allocations, which has a significant impact on performance
+ */
+static struct omap_hwmod_link *linkspace;
+
+/*
+ * free_ls, max_ls: array indexes into linkspace; representing the
+ * next free struct omap_hwmod_link index, and the maximum number of
+ * struct omap_hwmod_link records allocated (respectively)
+ */
+static unsigned short free_ls, max_ls, ls_supp;
/* Private functions */
+/**
+ * _fetch_next_ocp_if - return the next OCP interface in a list
+ * @p: ptr to a ptr to the list_head inside the ocp_if to return
+ * @i: pointer to the index of the element pointed to by @p in the list
+ *
+ * Return a pointer to the struct omap_hwmod_ocp_if record
+ * containing the struct list_head pointed to by @p, and increment
+ * @p such that a future call to this routine will return the next
+ * record.
+ */
+static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p,
+ int *i)
+{
+ struct omap_hwmod_ocp_if *oi;
+
+ oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if;
+ *p = (*p)->next;
+
+ *i = *i + 1;
+
+ return oi;
+}
+
/**
* _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
* @oh: struct omap_hwmod *
*/
static int _init_interface_clks(struct omap_hwmod *oh)
{
+ struct omap_hwmod_ocp_if *os;
+ struct list_head *p;
struct clk *c;
- int i;
+ int i = 0;
int ret = 0;
- if (oh->slaves_cnt == 0)
- return 0;
-
- for (i = 0; i < oh->slaves_cnt; i++) {
- struct omap_hwmod_ocp_if *os = oh->slaves[i];
+ p = oh->slave_ports.next;
+ while (i < oh->slaves_cnt) {
+ os = _fetch_next_ocp_if(&p, &i);
if (!os->clk)
continue;
*/
static int _enable_clocks(struct omap_hwmod *oh)
{
- int i;
+ struct omap_hwmod_ocp_if *os;
+ struct list_head *p;
+ int i = 0;
pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
if (oh->_clk)
clk_enable(oh->_clk);
- if (oh->slaves_cnt > 0) {
- for (i = 0; i < oh->slaves_cnt; i++) {
- struct omap_hwmod_ocp_if *os = oh->slaves[i];
- struct clk *c = os->_clk;
+ p = oh->slave_ports.next;
- if (c && (os->flags & OCPIF_SWSUP_IDLE))
- clk_enable(c);
- }
+ while (i < oh->slaves_cnt) {
+ os = _fetch_next_ocp_if(&p, &i);
+
+ if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
+ clk_enable(os->_clk);
}
/* The opt clocks are controlled by the device driver. */
*/
static int _disable_clocks(struct omap_hwmod *oh)
{
- int i;
+ struct omap_hwmod_ocp_if *os;
+ struct list_head *p;
+ int i = 0;
pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
if (oh->_clk)
clk_disable(oh->_clk);
- if (oh->slaves_cnt > 0) {
- for (i = 0; i < oh->slaves_cnt; i++) {
- struct omap_hwmod_ocp_if *os = oh->slaves[i];
- struct clk *c = os->_clk;
+ p = oh->slave_ports.next;
- if (c && (os->flags & OCPIF_SWSUP_IDLE))
- clk_disable(c);
- }
+ while (i < oh->slaves_cnt) {
+ os = _fetch_next_ocp_if(&p, &i);
+
+ if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
+ clk_disable(os->_clk);
}
/* The opt clocks are controlled by the device driver. */
oh->prcm.omap4.clkctrl_offs);
}
-/**
- * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
- * @oh: struct omap_hwmod *
- *
- * Disable the PRCM module mode related to the hwmod @oh.
- * Return EINVAL if the modulemode is not supported and 0 in case of success.
- */
-static int _omap4_disable_module(struct omap_hwmod *oh)
-{
- int v;
-
- /* The module mode does not exist prior OMAP4 */
- if (!cpu_is_omap44xx())
- return -EINVAL;
-
- if (!oh->clkdm || !oh->prcm.omap4.modulemode)
- return -EINVAL;
-
- pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
-
- omap4_cminst_module_disable(oh->clkdm->prcm_partition,
- oh->clkdm->cm_inst,
- oh->clkdm->clkdm_offs,
- oh->prcm.omap4.clkctrl_offs);
-
- v = _omap4_wait_target_disable(oh);
- if (v)
- pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
- oh->name);
-
- return 0;
-}
-
/**
* _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
* @oh: struct omap_hwmod *oh
}
/**
- * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
- * @oh: struct omap_hwmod *
+ * _get_mpu_irq_by_name - fetch MPU interrupt line number by name
+ * @oh: struct omap_hwmod * to operate on
+ * @name: pointer to the name of the MPU interrupt number to fetch (optional)
+ * @irq: pointer to an unsigned int to store the MPU IRQ number to
*
- * Returns the array index of the OCP slave port that the MPU
- * addresses the device on, or -EINVAL upon error or not found.
+ * Retrieve a MPU hardware IRQ line number named by @name associated
+ * with the IP block pointed to by @oh. The IRQ number will be filled
+ * into the address pointed to by @dma. When @name is non-null, the
+ * IRQ line number associated with the named entry will be returned.
+ * If @name is null, the first matching entry will be returned. Data
+ * order is not meaningful in hwmod data, so callers are strongly
+ * encouraged to use a non-null @name whenever possible to avoid
+ * unpredictable effects if hwmod data is later added that causes data
+ * ordering to change. Returns 0 upon success or a negative error
+ * code upon error.
*/
-static int __init _find_mpu_port_index(struct omap_hwmod *oh)
+static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name,
+ unsigned int *irq)
{
int i;
- int found = 0;
+ bool found = false;
- if (!oh || oh->slaves_cnt == 0)
- return -EINVAL;
+ if (!oh->mpu_irqs)
+ return -ENOENT;
- for (i = 0; i < oh->slaves_cnt; i++) {
- struct omap_hwmod_ocp_if *os = oh->slaves[i];
+ i = 0;
+ while (oh->mpu_irqs[i].irq != -1) {
+ if (name == oh->mpu_irqs[i].name ||
+ !strcmp(name, oh->mpu_irqs[i].name)) {
+ found = true;
+ break;
+ }
+ i++;
+ }
- if (os->user & OCP_USER_MPU) {
- found = 1;
+ if (!found)
+ return -ENOENT;
+
+ *irq = oh->mpu_irqs[i].irq;
+
+ return 0;
+}
+
+/**
+ * _get_sdma_req_by_name - fetch SDMA request line ID by name
+ * @oh: struct omap_hwmod * to operate on
+ * @name: pointer to the name of the SDMA request line to fetch (optional)
+ * @dma: pointer to an unsigned int to store the request line ID to
+ *
+ * Retrieve an SDMA request line ID named by @name on the IP block
+ * pointed to by @oh. The ID will be filled into the address pointed
+ * to by @dma. When @name is non-null, the request line ID associated
+ * with the named entry will be returned. If @name is null, the first
+ * matching entry will be returned. Data order is not meaningful in
+ * hwmod data, so callers are strongly encouraged to use a non-null
+ * @name whenever possible to avoid unpredictable effects if hwmod
+ * data is later added that causes data ordering to change. Returns 0
+ * upon success or a negative error code upon error.
+ */
+static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name,
+ unsigned int *dma)
+{
+ int i;
+ bool found = false;
+
+ if (!oh->sdma_reqs)
+ return -ENOENT;
+
+ i = 0;
+ while (oh->sdma_reqs[i].dma_req != -1) {
+ if (name == oh->sdma_reqs[i].name ||
+ !strcmp(name, oh->sdma_reqs[i].name)) {
+ found = true;
break;
}
+ i++;
}
- if (found)
- pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n",
- oh->name, i);
- else
- pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
- oh->name);
+ if (!found)
+ return -ENOENT;
+
+ *dma = oh->sdma_reqs[i].dma_req;
- return (found) ? i : -EINVAL;
+ return 0;
}
/**
- * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU
- * @oh: struct omap_hwmod *
+ * _get_addr_space_by_name - fetch address space start & end by name
+ * @oh: struct omap_hwmod * to operate on
+ * @name: pointer to the name of the address space to fetch (optional)
+ * @pa_start: pointer to a u32 to store the starting address to
+ * @pa_end: pointer to a u32 to store the ending address to
*
- * Return the virtual address of the base of the register target of
- * device @oh, or NULL on error.
+ * Retrieve address space start and end addresses for the IP block
+ * pointed to by @oh. The data will be filled into the addresses
+ * pointed to by @pa_start and @pa_end. When @name is non-null, the
+ * address space data associated with the named entry will be
+ * returned. If @name is null, the first matching entry will be
+ * returned. Data order is not meaningful in hwmod data, so callers
+ * are strongly encouraged to use a non-null @name whenever possible
+ * to avoid unpredictable effects if hwmod data is later added that
+ * causes data ordering to change. Returns 0 upon success or a
+ * negative error code upon error.
*/
-static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
+static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
+ u32 *pa_start, u32 *pa_end)
{
+ int i, j;
struct omap_hwmod_ocp_if *os;
- struct omap_hwmod_addr_space *mem;
- int i = 0, found = 0;
- void __iomem *va_start;
+ struct list_head *p = NULL;
+ bool found = false;
+
+ p = oh->slave_ports.next;
+
+ i = 0;
+ while (i < oh->slaves_cnt) {
+ os = _fetch_next_ocp_if(&p, &i);
+
+ if (!os->addr)
+ return -ENOENT;
+
+ j = 0;
+ while (os->addr[j].pa_start != os->addr[j].pa_end) {
+ if (name == os->addr[j].name ||
+ !strcmp(name, os->addr[j].name)) {
+ found = true;
+ break;
+ }
+ j++;
+ }
+
+ if (found)
+ break;
+ }
+
+ if (!found)
+ return -ENOENT;
+
+ *pa_start = os->addr[j].pa_start;
+ *pa_end = os->addr[j].pa_end;
+
+ return 0;
+}
+
+/**
+ * _save_mpu_port_index - find and save the index to @oh's MPU port
+ * @oh: struct omap_hwmod *
+ *
+ * Determines the array index of the OCP slave port that the MPU uses
+ * to address the device, and saves it into the struct omap_hwmod.
+ * Intended to be called during hwmod registration only. No return
+ * value.
+ */
+static void __init _save_mpu_port_index(struct omap_hwmod *oh)
+{
+ struct omap_hwmod_ocp_if *os = NULL;
+ struct list_head *p;
+ int i = 0;
+
+ if (!oh)
+ return;
- if (!oh || oh->slaves_cnt == 0)
+ oh->_int_flags |= _HWMOD_NO_MPU_PORT;
+
+ p = oh->slave_ports.next;
+
+ while (i < oh->slaves_cnt) {
+ os = _fetch_next_ocp_if(&p, &i);
+ if (os->user & OCP_USER_MPU) {
+ oh->_mpu_port = os;
+ oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
+ break;
+ }
+ }
+
+ return;
+}
+
+/**
+ * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU
+ * @oh: struct omap_hwmod *
+ *
+ * Given a pointer to a struct omap_hwmod record @oh, return a pointer
+ * to the struct omap_hwmod_ocp_if record that is used by the MPU to
+ * communicate with the IP block. This interface need not be directly
+ * connected to the MPU (and almost certainly is not), but is directly
+ * connected to the IP block represented by @oh. Returns a pointer
+ * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon
+ * error or if there does not appear to be a path from the MPU to this
+ * IP block.
+ */
+static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
+{
+ if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
return NULL;
- os = oh->slaves[index];
+ return oh->_mpu_port;
+};
+
+/**
+ * _find_mpu_rt_addr_space - return MPU register target address space for @oh
+ * @oh: struct omap_hwmod *
+ *
+ * Returns a pointer to the struct omap_hwmod_addr_space record representing
+ * the register target MPU address space; or returns NULL upon error.
+ */
+static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh)
+{
+ struct omap_hwmod_ocp_if *os;
+ struct omap_hwmod_addr_space *mem;
+ int found = 0, i = 0;
- if (!os->addr)
+ os = _find_mpu_rt_port(oh);
+ if (!os || !os->addr)
return NULL;
do {
found = 1;
} while (!found && mem->pa_start != mem->pa_end);
- if (found) {
- va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
- if (!va_start) {
- pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
- return NULL;
- }
- pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
- oh->name, va_start);
- } else {
- pr_debug("omap_hwmod: %s: no MPU register target found\n",
- oh->name);
- }
-
- return (found) ? va_start : NULL;
+ return (found) ? mem : NULL;
}
/**
if (!oh)
return -EINVAL;
- if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+ if (oh->flags & HWMOD_NO_IDLEST)
return 0;
- os = oh->slaves[oh->_mpu_port_index];
-
- if (oh->flags & HWMOD_NO_IDLEST)
+ os = _find_mpu_rt_port(oh);
+ if (!os)
return 0;
/* XXX check module SIDLEMODE */
}
}
+/**
+ * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
+ * @oh: struct omap_hwmod *
+ *
+ * If any hardreset line associated with @oh is asserted, then return true.
+ * Otherwise, if @oh has no hardreset lines associated with it, or if
+ * no hardreset lines associated with @oh are asserted, then return false.
+ * This function is used to avoid executing some parts of the IP block
+ * enable/disable sequence if a hardreset line is set.
+ */
+static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
+{
+ int i;
+
+ if (oh->rst_lines_cnt == 0)
+ return false;
+
+ for (i = 0; i < oh->rst_lines_cnt; i++)
+ if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
+ return true;
+
+ return false;
+}
+
+/**
+ * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
+ * @oh: struct omap_hwmod *
+ *
+ * Disable the PRCM module mode related to the hwmod @oh.
+ * Return EINVAL if the modulemode is not supported and 0 in case of success.
+ */
+static int _omap4_disable_module(struct omap_hwmod *oh)
+{
+ int v;
+
+ /* The module mode does not exist prior OMAP4 */
+ if (!cpu_is_omap44xx())
+ return -EINVAL;
+
+ if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+ return -EINVAL;
+
+ pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
+
+ omap4_cminst_module_disable(oh->clkdm->prcm_partition,
+ oh->clkdm->cm_inst,
+ oh->clkdm->clkdm_offs,
+ oh->prcm.omap4.clkctrl_offs);
+
+ if (_are_any_hardreset_lines_asserted(oh))
+ return 0;
+
+ v = _omap4_wait_target_disable(oh);
+ if (v)
+ pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+ oh->name);
+
+ return 0;
+}
+
/**
* _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
* @oh: struct omap_hwmod *
*
* Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be
- * enabled for this to work. Returns -EINVAL if the hwmod cannot be
- * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
- * the module did not reset in time, or 0 upon success.
+ * enabled for this to work. Returns -ENOENT if the hwmod cannot be
+ * reset this way, -EINVAL if the hwmod is in the wrong state,
+ * -ETIMEDOUT if the module did not reset in time, or 0 upon success.
*
* In OMAP3 a specific SYSSTATUS register is used to get the reset status.
* Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
if (!oh->class->sysc ||
!(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
- return -EINVAL;
+ return -ENOENT;
/* clocks must be on for this operation */
if (oh->_state != _HWMOD_STATE_ENABLED) {
* _reset - reset an omap_hwmod
* @oh: struct omap_hwmod *
*
- * Resets an omap_hwmod @oh. The default software reset mechanism for
- * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET
- * bit. However, some hwmods cannot be reset via this method: some
- * are not targets and therefore have no OCP header registers to
- * access; others (like the IVA) have idiosyncratic reset sequences.
- * So for these relatively rare cases, custom reset code can be
- * supplied in the struct omap_hwmod_class .reset function pointer.
- * Passes along the return value from either _reset() or the custom
- * reset function - these must return -EINVAL if the hwmod cannot be
- * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
- * the module did not reset in time, or 0 upon success.
+ * Resets an omap_hwmod @oh. If the module has a custom reset
+ * function pointer defined, then call it to reset the IP block, and
+ * pass along its return value to the caller. Otherwise, if the IP
+ * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield
+ * associated with it, call a function to reset the IP block via that
+ * method, and pass along the return value to the caller. Finally, if
+ * the IP block has some hardreset lines associated with it, assert
+ * all of those, but do _not_ deassert them. (This is because driver
+ * authors have expressed an apparent requirement to control the
+ * deassertion of the hardreset lines themselves.)
+ *
+ * The default software reset mechanism for most OMAP IP blocks is
+ * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some
+ * hwmods cannot be reset via this method. Some are not targets and
+ * therefore have no OCP header registers to access. Others (like the
+ * IVA) have idiosyncratic reset sequences. So for these relatively
+ * rare cases, custom reset code can be supplied in the struct
+ * omap_hwmod_class .reset function pointer. Passes along the return
+ * value from either _ocp_softreset() or the custom reset function -
+ * these must return -EINVAL if the hwmod cannot be reset this way or
+ * if the hwmod is in the wrong state, -ETIMEDOUT if the module did
+ * not reset in time, or 0 upon success.
*/
static int _reset(struct omap_hwmod *oh)
{
- int ret;
+ int i, r;
pr_debug("omap_hwmod: %s: resetting\n", oh->name);
- ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
+ if (oh->class->reset) {
+ r = oh->class->reset(oh);
+ } else {
+ if (oh->rst_lines_cnt > 0) {
+ for (i = 0; i < oh->rst_lines_cnt; i++)
+ _assert_hardreset(oh, oh->rst_lines[i].name);
+ return 0;
+ } else {
+ r = _ocp_softreset(oh);
+ if (r == -ENOENT)
+ r = 0;
+ }
+ }
+ /*
+ * OCP_SYSCONFIG bits need to be reprogrammed after a
+ * softreset. The _enable() function should be split to avoid
+ * the rewrite of the OCP_SYSCONFIG register.
+ */
if (oh->class->sysc) {
_update_sysc_cache(oh);
_enable_sysc(oh);
}
- return ret;
+ return r;
}
/**
pr_debug("omap_hwmod: %s: enabling\n", oh->name);
/*
- * hwmods with HWMOD_INIT_NO_IDLE flag set are left
- * in enabled state at init.
- * Now that someone is really trying to enable them,
- * just ensure that the hwmod mux is set.
+ * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
+ * state at init. Now that someone is really trying to enable
+ * them, just ensure that the hwmod mux is set.
*/
if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
/*
return -EINVAL;
}
-
/*
- * If an IP contains only one HW reset line, then de-assert it in order
- * to allow the module state transition. Otherwise the PRCM will return
- * Intransition status, and the init will failed.
+ * If an IP block contains HW reset lines and any of them are
+ * asserted, we let integration code associated with that
+ * block handle the enable. We've received very little
+ * information on what those driver authors need, and until
+ * detailed information is provided and the driver code is
+ * posted to the public lists, this is probably the best we
+ * can do.
*/
- if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
- oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
- _deassert_hardreset(oh, oh->rst_lines[0].name);
+ if (_are_any_hardreset_lines_asserted(oh))
+ return 0;
/* Mux pins for device runtime if populated */
if (oh->mux && (!oh->mux->enabled ||
return -EINVAL;
}
+ if (_are_any_hardreset_lines_asserted(oh))
+ return 0;
+
if (oh->class->sysc)
_idle_sysc(oh);
_del_initiator_dep(oh, mpu_oh);
*/
static int _shutdown(struct omap_hwmod *oh)
{
- int ret;
+ int ret, i;
u8 prev_state;
if (oh->_state != _HWMOD_STATE_IDLE &&
return -EINVAL;
}
+ if (_are_any_hardreset_lines_asserted(oh))
+ return 0;
+
pr_debug("omap_hwmod: %s: disabling\n", oh->name);
if (oh->class->pre_shutdown) {
}
/* XXX Should this code also force-disable the optional clocks? */
- /*
- * If an IP contains only one HW reset line, then assert it
- * after disabling the clocks and before shutting down the IP.
- */
- if (oh->rst_lines_cnt == 1)
- _assert_hardreset(oh, oh->rst_lines[0].name);
+ for (i = 0; i < oh->rst_lines_cnt; i++)
+ _assert_hardreset(oh, oh->rst_lines[i].name);
/* Mux pins to safe mode or use populated off mode values */
if (oh->mux)
}
/**
- * _setup - do initial configuration of omap_hwmod
- * @oh: struct omap_hwmod *
+ * _init_mpu_rt_base - populate the virtual address for a hwmod
+ * @oh: struct omap_hwmod * to locate the virtual address
*
- * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register. Returns 0.
+ * Cache the virtual address used by the MPU to access this IP block's
+ * registers. This address is needed early so the OCP registers that
+ * are part of the device's address space can be ioremapped properly.
+ * No return value.
*/
-static int _setup(struct omap_hwmod *oh, void *data)
+static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
{
- int i, r;
- u8 postsetup_state;
+ struct omap_hwmod_addr_space *mem;
+ void __iomem *va_start;
+
+ if (!oh)
+ return;
+
+ _save_mpu_port_index(oh);
- if (oh->_state != _HWMOD_STATE_CLKS_INITED)
+ if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+ return;
+
+ mem = _find_mpu_rt_addr_space(oh);
+ if (!mem) {
+ pr_debug("omap_hwmod: %s: no MPU register target found\n",
+ oh->name);
+ return;
+ }
+
+ va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
+ if (!va_start) {
+ pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
+ return;
+ }
+
+ pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
+ oh->name, va_start);
+
+ oh->_mpu_rt_va = va_start;
+}
+
+/**
+ * _init - initialize internal data for the hwmod @oh
+ * @oh: struct omap_hwmod *
+ * @n: (unused)
+ *
+ * Look up the clocks and the address space used by the MPU to access
+ * registers belonging to the hwmod @oh. @oh must already be
+ * registered at this point. This is the first of two phases for
+ * hwmod initialization. Code called here does not touch any hardware
+ * registers, it simply prepares internal data structures. Returns 0
+ * upon success or if the hwmod isn't registered, or -EINVAL upon
+ * failure.
+ */
+static int __init _init(struct omap_hwmod *oh, void *data)
+{
+ int r;
+
+ if (oh->_state != _HWMOD_STATE_REGISTERED)
return 0;
- /* Set iclk autoidle mode */
- if (oh->slaves_cnt > 0) {
- for (i = 0; i < oh->slaves_cnt; i++) {
- struct omap_hwmod_ocp_if *os = oh->slaves[i];
- struct clk *c = os->_clk;
+ _init_mpu_rt_base(oh, NULL);
- if (!c)
- continue;
+ r = _init_clocks(oh, NULL);
+ if (IS_ERR_VALUE(r)) {
+ WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
+ return -EINVAL;
+ }
- if (os->flags & OCPIF_SWSUP_IDLE) {
- /* XXX omap_iclk_deny_idle(c); */
- } else {
- /* XXX omap_iclk_allow_idle(c); */
- clk_enable(c);
- }
+ oh->_state = _HWMOD_STATE_INITIALIZED;
+
+ return 0;
+}
+
+/**
+ * _setup_iclk_autoidle - configure an IP block's interface clocks
+ * @oh: struct omap_hwmod *
+ *
+ * Set up the module's interface clocks. XXX This function is still mostly
+ * a stub; implementing this properly requires iclk autoidle usecounting in
+ * the clock code. No return value.
+ */
+static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
+{
+ struct omap_hwmod_ocp_if *os;
+ struct list_head *p;
+ int i = 0;
+ if (oh->_state != _HWMOD_STATE_INITIALIZED)
+ return;
+
+ p = oh->slave_ports.next;
+
+ while (i < oh->slaves_cnt) {
+ os = _fetch_next_ocp_if(&p, &i);
+ if (!os->_clk)
+ continue;
+
+ if (os->flags & OCPIF_SWSUP_IDLE) {
+ /* XXX omap_iclk_deny_idle(c); */
+ } else {
+ /* XXX omap_iclk_allow_idle(c); */
+ clk_enable(os->_clk);
}
}
- oh->_state = _HWMOD_STATE_INITIALIZED;
+ return;
+}
- /*
- * In the case of hwmod with hardreset that should not be
- * de-assert at boot time, we have to keep the module
- * initialized, because we cannot enable it properly with the
- * reset asserted. Exit without warning because that behavior is
- * expected.
- */
- if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
- return 0;
+/**
+ * _setup_reset - reset an IP block during the setup process
+ * @oh: struct omap_hwmod *
+ *
+ * Reset the IP block corresponding to the hwmod @oh during the setup
+ * process. The IP block is first enabled so it can be successfully
+ * reset. Returns 0 upon success or a negative error code upon
+ * failure.
+ */
+static int __init _setup_reset(struct omap_hwmod *oh)
+{
+ int r;
- r = _enable(oh);
- if (r) {
- pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
- oh->name, oh->_state);
- return 0;
+ if (oh->_state != _HWMOD_STATE_INITIALIZED)
+ return -EINVAL;
+
+ if (oh->rst_lines_cnt == 0) {
+ r = _enable(oh);
+ if (r) {
+ pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
+ oh->name, oh->_state);
+ return -EINVAL;
+ }
}
if (!(oh->flags & HWMOD_INIT_NO_RESET))
- _reset(oh);
+ r = _reset(oh);
+
+ return r;
+}
+
+/**
+ * _setup_postsetup - transition to the appropriate state after _setup
+ * @oh: struct omap_hwmod *
+ *
+ * Place an IP block represented by @oh into a "post-setup" state --
+ * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that
+ * this function is called at the end of _setup().) The postsetup
+ * state for an IP block can be changed by calling
+ * omap_hwmod_enter_postsetup_state() early in the boot process,
+ * before one of the omap_hwmod_setup*() functions are called for the
+ * IP block.
+ *
+ * The IP block stays in this state until a PM runtime-based driver is
+ * loaded for that IP block. A post-setup state of IDLE is
+ * appropriate for almost all IP blocks with runtime PM-enabled
+ * drivers, since those drivers are able to enable the IP block. A
+ * post-setup state of ENABLED is appropriate for kernels with PM
+ * runtime disabled. The DISABLED state is appropriate for unusual IP
+ * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers
+ * included, since the WDTIMER starts running on reset and will reset
+ * the MPU if left active.
+ *
+ * This post-setup mechanism is deprecated. Once all of the OMAP
+ * drivers have been converted to use PM runtime, and all of the IP
+ * block data and interconnect data is available to the hwmod code, it
+ * should be possible to replace this mechanism with a "lazy reset"
+ * arrangement. In a "lazy reset" setup, each IP block is enabled
+ * when the driver first probes, then all remaining IP blocks without
+ * drivers are either shut down or enabled after the drivers have
+ * loaded. However, this cannot take place until the above
+ * preconditions have been met, since otherwise the late reset code
+ * has no way of knowing which IP blocks are in use by drivers, and
+ * which ones are unused.
+ *
+ * No return value.
+ */
+static void __init _setup_postsetup(struct omap_hwmod *oh)
+{
+ u8 postsetup_state;
+
+ if (oh->rst_lines_cnt > 0)
+ return;
postsetup_state = oh->_postsetup_state;
if (postsetup_state == _HWMOD_STATE_UNKNOWN)
WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
oh->name, postsetup_state);
+ return;
+}
+
+/**
+ * _setup - prepare IP block hardware for use
+ * @oh: struct omap_hwmod *
+ * @n: (unused, pass NULL)
+ *
+ * Configure the IP block represented by @oh. This may include
+ * enabling the IP block, resetting it, and placing it into a
+ * post-setup state, depending on the type of IP block and applicable
+ * flags. IP blocks are reset to prevent any previous configuration
+ * by the bootloader or previous operating system from interfering
+ * with power management or other parts of the system. The reset can
+ * be avoided; see omap_hwmod_no_setup_reset(). This is the second of
+ * two phases for hwmod initialization. Code called here generally
+ * affects the IP block hardware, or system integration hardware
+ * associated with the IP block. Returns 0.
+ */
+static int __init _setup(struct omap_hwmod *oh, void *data)
+{
+ if (oh->_state != _HWMOD_STATE_INITIALIZED)
+ return 0;
+
+ _setup_iclk_autoidle(oh);
+
+ if (!_setup_reset(oh))
+ _setup_postsetup(oh);
+
return 0;
}
*/
static int __init _register(struct omap_hwmod *oh)
{
- int ms_id;
-
if (!oh || !oh->name || !oh->class || !oh->class->name ||
(oh->_state != _HWMOD_STATE_UNKNOWN))
return -EINVAL;
if (_lookup(oh->name))
return -EEXIST;
- ms_id = _find_mpu_port_index(oh);
- if (!IS_ERR_VALUE(ms_id))
- oh->_mpu_port_index = ms_id;
- else
- oh->_int_flags |= _HWMOD_NO_MPU_PORT;
-
list_add_tail(&oh->node, &omap_hwmod_list);
+ INIT_LIST_HEAD(&oh->master_ports);
+ INIT_LIST_HEAD(&oh->slave_ports);
spin_lock_init(&oh->_lock);
oh->_state = _HWMOD_STATE_REGISTERED;
return 0;
}
+/**
+ * _alloc_links - return allocated memory for hwmod links
+ * @ml: pointer to a struct omap_hwmod_link * for the master link
+ * @sl: pointer to a struct omap_hwmod_link * for the slave link
+ *
+ * Return pointers to two struct omap_hwmod_link records, via the
+ * addresses pointed to by @ml and @sl. Will first attempt to return
+ * memory allocated as part of a large initial block, but if that has
+ * been exhausted, will allocate memory itself. Since ideally this
+ * second allocation path will never occur, the number of these
+ * 'supplemental' allocations will be logged when debugging is
+ * enabled. Returns 0.
+ */
+static int __init _alloc_links(struct omap_hwmod_link **ml,
+ struct omap_hwmod_link **sl)
+{
+ unsigned int sz;
+
+ if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) {
+ *ml = &linkspace[free_ls++];
+ *sl = &linkspace[free_ls++];
+ return 0;
+ }
+
+ sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF;
+
+ *sl = NULL;
+ *ml = alloc_bootmem(sz);
+
+ memset(*ml, 0, sz);
+
+ *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link);
+
+ ls_supp++;
+ pr_debug("omap_hwmod: supplemental link allocations needed: %d\n",
+ ls_supp * LINKS_PER_OCP_IF);
+
+ return 0;
+};
+
+/**
+ * _add_link - add an interconnect between two IP blocks
+ * @oi: pointer to a struct omap_hwmod_ocp_if record
+ *
+ * Add struct omap_hwmod_link records connecting the master IP block
+ * specified in @oi->master to @oi, and connecting the slave IP block
+ * specified in @oi->slave to @oi. This code is assumed to run before
+ * preemption or SMP has been enabled, thus avoiding the need for
+ * locking in this code. Changes to this assumption will require
+ * additional locking. Returns 0.
+ */
+static int __init _add_link(struct omap_hwmod_ocp_if *oi)
+{
+ struct omap_hwmod_link *ml, *sl;
+
+ pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
+ oi->slave->name);
+
+ _alloc_links(&ml, &sl);
+
+ ml->ocp_if = oi;
+ INIT_LIST_HEAD(&ml->node);
+ list_add(&ml->node, &oi->master->master_ports);
+ oi->master->masters_cnt++;
+
+ sl->ocp_if = oi;
+ INIT_LIST_HEAD(&sl->node);
+ list_add(&sl->node, &oi->slave->slave_ports);
+ oi->slave->slaves_cnt++;
+
+ return 0;
+}
+
+/**
+ * _register_link - register a struct omap_hwmod_ocp_if
+ * @oi: struct omap_hwmod_ocp_if *
+ *
+ * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it
+ * has already been registered; -EINVAL if @oi is NULL or if the
+ * record pointed to by @oi is missing required fields; or 0 upon
+ * success.
+ *
+ * XXX The data should be copied into bootmem, so the original data
+ * should be marked __initdata and freed after init. This would allow
+ * unneeded omap_hwmods to be freed on multi-OMAP configurations.
+ */
+static int __init _register_link(struct omap_hwmod_ocp_if *oi)
+{
+ if (!oi || !oi->master || !oi->slave || !oi->user)
+ return -EINVAL;
+
+ if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED)
+ return -EEXIST;
+
+ pr_debug("omap_hwmod: registering link from %s to %s\n",
+ oi->master->name, oi->slave->name);
+
+ /*
+ * Register the connected hwmods, if they haven't been
+ * registered already
+ */
+ if (oi->master->_state != _HWMOD_STATE_REGISTERED)
+ _register(oi->master);
+
+ if (oi->slave->_state != _HWMOD_STATE_REGISTERED)
+ _register(oi->slave);
+
+ _add_link(oi);
+
+ oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED;
+
+ return 0;
+}
+
+/**
+ * _alloc_linkspace - allocate large block of hwmod links
+ * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count
+ *
+ * Allocate a large block of struct omap_hwmod_link records. This
+ * improves boot time significantly by avoiding the need to allocate
+ * individual records one by one. If the number of records to
+ * allocate in the block hasn't been manually specified, this function
+ * will count the number of struct omap_hwmod_ocp_if records in @ois
+ * and use that to determine the allocation size. For SoC families
+ * that require multiple list registrations, such as OMAP3xxx, this
+ * estimation process isn't optimal, so manual estimation is advised
+ * in those cases. Returns -EEXIST if the allocation has already occurred
+ * or 0 upon success.
+ */
+static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
+{
+ unsigned int i = 0;
+ unsigned int sz;
+
+ if (linkspace) {
+ WARN(1, "linkspace already allocated\n");
+ return -EEXIST;
+ }
+
+ if (max_ls == 0)
+ while (ois[i++])
+ max_ls += LINKS_PER_OCP_IF;
+
+ sz = sizeof(struct omap_hwmod_link) * max_ls;
+
+ pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n",
+ __func__, sz, max_ls);
+
+ linkspace = alloc_bootmem(sz);
+
+ memset(linkspace, 0, sz);
+
+ return 0;
+}
/* Public functions */
}
/**
- * omap_hwmod_register - register an array of hwmods
- * @ohs: pointer to an array of omap_hwmods to register
+ * omap_hwmod_register_links - register an array of hwmod links
+ * @ois: pointer to an array of omap_hwmod_ocp_if to register
*
* Intended to be called early in boot before the clock framework is
- * initialized. If @ohs is not null, will register all omap_hwmods
- * listed in @ohs that are valid for this chip. Returns 0.
+ * initialized. If @ois is not null, will register all omap_hwmods
+ * listed in @ois that are valid for this chip. Returns 0.
*/
-int __init omap_hwmod_register(struct omap_hwmod **ohs)
+int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
{
int r, i;
- if (!ohs)
+ if (!ois)
return 0;
+ if (!linkspace) {
+ if (_alloc_linkspace(ois)) {
+ pr_err("omap_hwmod: could not allocate link space\n");
+ return -ENOMEM;
+ }
+ }
+
i = 0;
do {
- r = _register(ohs[i]);
- WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
- r);
- } while (ohs[++i]);
+ r = _register_link(ois[i]);
+ WARN(r && r != -EEXIST,
+ "omap_hwmod: _register_link(%s -> %s) returned %d\n",
+ ois[i]->master->name, ois[i]->slave->name, r);
+ } while (ois[++i]);
return 0;
}
-/*
- * _populate_mpu_rt_base - populate the virtual address for a hwmod
+/**
+ * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
+ * @oh: pointer to the hwmod currently being set up (usually not the MPU)
*
- * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
- * Assumes the caller takes care of locking if needed.
+ * If the hwmod data corresponding to the MPU subsystem IP block
+ * hasn't been initialized and set up yet, do so now. This must be
+ * done first since sleep dependencies may be added from other hwmods
+ * to the MPU. Intended to be called only by omap_hwmod_setup*(). No
+ * return value.
*/
-static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
{
- if (oh->_state != _HWMOD_STATE_REGISTERED)
- return 0;
-
- if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
- return 0;
-
- oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
-
- return 0;
+ if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN)
+ pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
+ __func__, MPU_INITIATOR_NAME);
+ else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
+ omap_hwmod_setup_one(MPU_INITIATOR_NAME);
}
/**
* omap_hwmod_setup_one - set up a single hwmod
* @oh_name: const char * name of the already-registered hwmod to set up
*
- * Must be called after omap2_clk_init(). Resolves the struct clk
- * names to struct clk pointers for each registered omap_hwmod. Also
- * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon
- * success.
+ * Initialize and set up a single hwmod. Intended to be used for a
+ * small number of early devices, such as the timer IP blocks used for
+ * the scheduler clock. Must be called after omap2_clk_init().
+ * Resolves the struct clk names to struct clk pointers for each
+ * registered omap_hwmod. Also calls _setup() on each hwmod. Returns
+ * -EINVAL upon error or 0 upon success.
*/
int __init omap_hwmod_setup_one(const char *oh_name)
{
struct omap_hwmod *oh;
- int r;
pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
- if (!mpu_oh) {
- pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
- oh_name, MPU_INITIATOR_NAME);
- return -EINVAL;
- }
-
oh = _lookup(oh_name);
if (!oh) {
WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
return -EINVAL;
}
- if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
- omap_hwmod_setup_one(MPU_INITIATOR_NAME);
-
- r = _populate_mpu_rt_base(oh, NULL);
- if (IS_ERR_VALUE(r)) {
- WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
- return -EINVAL;
- }
-
- r = _init_clocks(oh, NULL);
- if (IS_ERR_VALUE(r)) {
- WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
- return -EINVAL;
- }
+ _ensure_mpu_hwmod_is_setup(oh);
+ _init(oh, NULL);
_setup(oh, NULL);
return 0;
}
/**
- * omap_hwmod_setup - do some post-clock framework initialization
+ * omap_hwmod_setup_all - set up all registered IP blocks
*
- * Must be called after omap2_clk_init(). Resolves the struct clk names
- * to struct clk pointers for each registered omap_hwmod. Also calls
- * _setup() on each hwmod. Returns 0 upon success.
+ * Initialize and set up all IP blocks registered with the hwmod code.
+ * Must be called after omap2_clk_init(). Resolves the struct clk
+ * names to struct clk pointers for each registered omap_hwmod. Also
+ * calls _setup() on each hwmod. Returns 0 upon success.
*/
static int __init omap_hwmod_setup_all(void)
{
- int r;
-
- if (!mpu_oh) {
- pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
- __func__, MPU_INITIATOR_NAME);
- return -EINVAL;
- }
-
- r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
-
- r = omap_hwmod_for_each(_init_clocks, NULL);
- WARN(IS_ERR_VALUE(r),
- "omap_hwmod: %s: _init_clocks failed\n", __func__);
+ _ensure_mpu_hwmod_is_setup(NULL);
+ omap_hwmod_for_each(_init, NULL);
omap_hwmod_for_each(_setup, NULL);
return 0;
return r;
}
+/*
+ * IP block data retrieval functions
+ */
+
/**
* omap_hwmod_count_resources - count number of struct resources needed by hwmod
* @oh: struct omap_hwmod *
*/
int omap_hwmod_count_resources(struct omap_hwmod *oh)
{
- int ret, i;
+ struct omap_hwmod_ocp_if *os;
+ struct list_head *p;
+ int ret;
+ int i = 0;
ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
- for (i = 0; i < oh->slaves_cnt; i++)
- ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
+ p = oh->slave_ports.next;
+
+ while (i < oh->slaves_cnt) {
+ os = _fetch_next_ocp_if(&p, &i);
+ ret += _count_ocp_if_addr_spaces(os);
+ }
return ret;
}
*/
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
{
- int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
+ struct omap_hwmod_ocp_if *os;
+ struct list_head *p;
+ int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt;
int r = 0;
/* For each IRQ, DMA, memory area, fill in array.*/
r++;
}
- for (i = 0; i < oh->slaves_cnt; i++) {
- struct omap_hwmod_ocp_if *os;
- int addr_cnt;
+ p = oh->slave_ports.next;
- os = oh->slaves[i];
+ i = 0;
+ while (i < oh->slaves_cnt) {
+ os = _fetch_next_ocp_if(&p, &i);
addr_cnt = _count_ocp_if_addr_spaces(os);
for (j = 0; j < addr_cnt; j++) {
return r;
}
+/**
+ * omap_hwmod_get_resource_byname - fetch IP block integration data by name
+ * @oh: struct omap_hwmod * to operate on
+ * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
+ * @name: pointer to the name of the data to fetch (optional)
+ * @rsrc: pointer to a struct resource, allocated by the caller
+ *
+ * Retrieve MPU IRQ, SDMA request line, or address space start/end
+ * data for the IP block pointed to by @oh. The data will be filled
+ * into a struct resource record pointed to by @rsrc. The struct
+ * resource must be allocated by the caller. When @name is non-null,
+ * the data associated with the matching entry in the IRQ/SDMA/address
+ * space hwmod data arrays will be returned. If @name is null, the
+ * first array entry will be returned. Data order is not meaningful
+ * in hwmod data, so callers are strongly encouraged to use a non-null
+ * @name whenever possible to avoid unpredictable effects if hwmod
+ * data is later added that causes data ordering to change. This
+ * function is only intended for use by OMAP core code. Device
+ * drivers should not call this function - the appropriate bus-related
+ * data accessor functions should be used instead. Returns 0 upon
+ * success or a negative error code upon error.
+ */
+int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
+ const char *name, struct resource *rsrc)
+{
+ int r;
+ unsigned int irq, dma;
+ u32 pa_start, pa_end;
+
+ if (!oh || !rsrc)
+ return -EINVAL;
+
+ if (type == IORESOURCE_IRQ) {
+ r = _get_mpu_irq_by_name(oh, name, &irq);
+ if (r)
+ return r;
+
+ rsrc->start = irq;
+ rsrc->end = irq;
+ } else if (type == IORESOURCE_DMA) {
+ r = _get_sdma_req_by_name(oh, name, &dma);
+ if (r)
+ return r;
+
+ rsrc->start = dma;
+ rsrc->end = dma;
+ } else if (type == IORESOURCE_MEM) {
+ r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end);
+ if (r)
+ return r;
+
+ rsrc->start = pa_start;
+ rsrc->end = pa_end;
+ } else {
+ return -EINVAL;
+ }
+
+ rsrc->flags = type;
+ rsrc->name = name;
+
+ return 0;
+}
+
/**
* omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
* @oh: struct omap_hwmod *
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
{
struct clk *c;
+ struct omap_hwmod_ocp_if *oi;
if (!oh)
return NULL;
if (oh->_clk) {
c = oh->_clk;
} else {
- if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+ oi = _find_mpu_rt_port(oh);
+ if (!oi)
return NULL;
- c = oh->slaves[oh->_mpu_port_index]->_clk;
+ c = oi->_clk;
}
if (!c->clkdm)
* @state: state that _setup() should leave the hwmod in
*
* Sets the hwmod state that @oh will enter at the end of _setup()
- * (called by omap_hwmod_setup_*()). Only valid to call between
- * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns
- * 0 upon success or -EINVAL if there is a problem with the arguments
- * or if the hwmod is in the wrong state.
+ * (called by omap_hwmod_setup_*()). See also the documentation
+ * for _setup_postsetup(), above. Returns 0 upon success or
+ * -EINVAL if there is a problem with the arguments or if the hwmod is
+ * in the wrong state.
*/
int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
{
* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
*
* Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
#include <plat/dmtimer.h>
#include <plat/l3_2xxx.h>
#include <plat/l4_2xxx.h>
+#include <plat/mmc.h>
#include "omap_hwmod_common_data.h"
/*
* OMAP2420 hardware module integration data
*
- * ALl of the data in this section should be autogeneratable from the
+ * All of the data in this section should be autogeneratable from the
* TI hardware database or other technical documentation. Data that
* is driver-specific or driver-kernel integration-specific belongs
* elsewhere.
*/
-static struct omap_hwmod omap2420_mpu_hwmod;
-static struct omap_hwmod omap2420_iva_hwmod;
-static struct omap_hwmod omap2420_l3_main_hwmod;
-static struct omap_hwmod omap2420_l4_core_hwmod;
-static struct omap_hwmod omap2420_dss_core_hwmod;
-static struct omap_hwmod omap2420_dss_dispc_hwmod;
-static struct omap_hwmod omap2420_dss_rfbi_hwmod;
-static struct omap_hwmod omap2420_dss_venc_hwmod;
-static struct omap_hwmod omap2420_wd_timer2_hwmod;
-static struct omap_hwmod omap2420_gpio1_hwmod;
-static struct omap_hwmod omap2420_gpio2_hwmod;
-static struct omap_hwmod omap2420_gpio3_hwmod;
-static struct omap_hwmod omap2420_gpio4_hwmod;
-static struct omap_hwmod omap2420_dma_system_hwmod;
-static struct omap_hwmod omap2420_mcspi1_hwmod;
-static struct omap_hwmod omap2420_mcspi2_hwmod;
-
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
- .master = &omap2420_l3_main_hwmod,
- .slave = &omap2420_l4_core_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
- .master = &omap2420_mpu_hwmod,
- .slave = &omap2420_l3_main_hwmod,
- .user = OCP_USER_MPU,
-};
-
-/* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
- &omap2420_mpu__l3_main,
-};
-
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
- .master = &omap2420_dss_core_hwmod,
- .slave = &omap2420_l3_main_hwmod,
- .fw = {
- .omap2 = {
- .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
- .flags = OMAP_FIREWALL_L3,
- }
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
- &omap2420_l3_main__l4_core,
-};
-
-/* L3 */
-static struct omap_hwmod omap2420_l3_main_hwmod = {
- .name = "l3_main",
- .class = &l3_hwmod_class,
- .masters = omap2420_l3_main_masters,
- .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters),
- .slaves = omap2420_l3_main_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves),
- .flags = HWMOD_NO_IDLEST,
-};
-
-static struct omap_hwmod omap2420_l4_wkup_hwmod;
-static struct omap_hwmod omap2420_uart1_hwmod;
-static struct omap_hwmod omap2420_uart2_hwmod;
-static struct omap_hwmod omap2420_uart3_hwmod;
-static struct omap_hwmod omap2420_i2c1_hwmod;
-static struct omap_hwmod omap2420_i2c2_hwmod;
-static struct omap_hwmod omap2420_mcbsp1_hwmod;
-static struct omap_hwmod omap2420_mcbsp2_hwmod;
-
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_mcspi1_hwmod,
- .clk = "mcspi1_ick",
- .addr = omap2_mcspi1_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_mcspi2_hwmod,
- .clk = "mcspi2_ick",
- .addr = omap2_mcspi2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_l4_wkup_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_uart1_hwmod,
- .clk = "uart1_ick",
- .addr = omap2xxx_uart1_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_uart2_hwmod,
- .clk = "uart2_ick",
- .addr = omap2xxx_uart2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_uart3_hwmod,
- .clk = "uart3_ick",
- .addr = omap2xxx_uart3_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_i2c1_hwmod,
- .clk = "i2c1_ick",
- .addr = omap2_i2c1_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_i2c2_hwmod,
- .clk = "i2c2_ick",
- .addr = omap2_i2c2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* Slave interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
- &omap2420_l3_main__l4_core,
-};
-
-/* Master interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
- &omap2420_l4_core__l4_wkup,
- &omap2_l4_core__uart1,
- &omap2_l4_core__uart2,
- &omap2_l4_core__uart3,
- &omap2420_l4_core__i2c1,
- &omap2420_l4_core__i2c2
-};
-
-/* L4 CORE */
-static struct omap_hwmod omap2420_l4_core_hwmod = {
- .name = "l4_core",
- .class = &l4_hwmod_class,
- .masters = omap2420_l4_core_masters,
- .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
- .slaves = omap2420_l4_core_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* Slave interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
- &omap2420_l4_core__l4_wkup,
-};
-
-/* Master interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
-};
-
-/* L4 WKUP */
-static struct omap_hwmod omap2420_l4_wkup_hwmod = {
- .name = "l4_wkup",
- .class = &l4_hwmod_class,
- .masters = omap2420_l4_wkup_masters,
- .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
- .slaves = omap2420_l4_wkup_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* Master interfaces on the MPU device */
-static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
- &omap2420_mpu__l3_main,
-};
-
-/* MPU */
-static struct omap_hwmod omap2420_mpu_hwmod = {
- .name = "mpu",
- .class = &mpu_hwmod_class,
- .main_clk = "mpu_ck",
- .masters = omap2420_mpu_masters,
- .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
-};
-
/*
- * IVA1 interface data
+ * IP blocks
*/
-/* IVA <- L3 interface */
-static struct omap_hwmod_ocp_if omap2420_l3__iva = {
- .master = &omap2420_l3_main_hwmod,
- .slave = &omap2420_iva_hwmod,
- .clk = "iva1_ifck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* IVA1 (IVA1) */
+static struct omap_hwmod_class iva1_hwmod_class = {
+ .name = "iva1",
};
-static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
- &omap2420_l3__iva,
+static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
+ { .name = "iva", .rst_shift = 8 },
};
-/*
- * IVA2 (IVA2)
- */
-
static struct omap_hwmod omap2420_iva_hwmod = {
.name = "iva",
- .class = &iva_hwmod_class,
- .masters = omap2420_iva_masters,
- .masters_cnt = ARRAY_SIZE(omap2420_iva_masters),
-};
-
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_PWM,
-};
-
-/* timer1 */
-static struct omap_hwmod omap2420_timer1_hwmod;
-
-static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
- {
- .pa_start = 0x48028000,
- .pa_end = 0x48028000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
- .master = &omap2420_l4_wkup_hwmod,
- .slave = &omap2420_timer1_hwmod,
- .clk = "gpt1_ick",
- .addr = omap2420_timer1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer1 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
- &omap2420_l4_wkup__timer1,
-};
-
-/* timer1 hwmod */
-static struct omap_hwmod omap2420_timer1_hwmod = {
- .name = "timer1",
- .mpu_irqs = omap2_timer1_mpu_irqs,
- .main_clk = "gpt1_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT1_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
- },
- },
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2420_timer1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
- .class = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer2 */
-static struct omap_hwmod omap2420_timer2_hwmod;
-
-/* l4_core -> timer2 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer2_hwmod,
- .clk = "gpt2_ick",
- .addr = omap2xxx_timer2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .class = &iva1_hwmod_class,
+ .clkdm_name = "iva1_clkdm",
+ .rst_lines = omap2420_iva_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
+ .main_clk = "iva1_ifck",
};
-/* timer2 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
- &omap2420_l4_core__timer2,
+/* DSP */
+static struct omap_hwmod_class dsp_hwmod_class = {
+ .name = "dsp",
};
-/* timer2 hwmod */
-static struct omap_hwmod omap2420_timer2_hwmod = {
- .name = "timer2",
- .mpu_irqs = omap2_timer2_mpu_irqs,
- .main_clk = "gpt2_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT2_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
- },
- },
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2420_timer2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
- .class = &omap2xxx_timer_hwmod_class,
+static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
+ { .name = "logic", .rst_shift = 0 },
+ { .name = "mmu", .rst_shift = 1 },
};
-/* timer3 */
-static struct omap_hwmod omap2420_timer3_hwmod;
-
-/* l4_core -> timer3 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer3_hwmod,
- .clk = "gpt3_ick",
- .addr = omap2xxx_timer3_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer3 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
- &omap2420_l4_core__timer3,
+static struct omap_hwmod omap2420_dsp_hwmod = {
+ .name = "dsp",
+ .class = &dsp_hwmod_class,
+ .clkdm_name = "dsp_clkdm",
+ .rst_lines = omap2420_dsp_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
+ .main_clk = "dsp_fck",
};
-/* timer3 hwmod */
-static struct omap_hwmod omap2420_timer3_hwmod = {
- .name = "timer3",
- .mpu_irqs = omap2_timer3_mpu_irqs,
- .main_clk = "gpt3_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT3_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
- },
- },
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2420_timer3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
- .class = &omap2xxx_timer_hwmod_class,
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x20,
+ .syss_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* timer4 */
-static struct omap_hwmod omap2420_timer4_hwmod;
-
-/* l4_core -> timer4 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer4_hwmod,
- .clk = "gpt4_ick",
- .addr = omap2xxx_timer4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_1,
+ .reset = &omap_i2c_reset,
};
-/* timer4 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
- &omap2420_l4_core__timer4,
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_NO_FIFO |
+ OMAP_I2C_FLAG_SIMPLE_CLOCK |
+ OMAP_I2C_FLAG_16BIT_DATA_REG |
+ OMAP_I2C_FLAG_BUS_SHIFT_2,
};
-/* timer4 hwmod */
-static struct omap_hwmod omap2420_timer4_hwmod = {
- .name = "timer4",
- .mpu_irqs = omap2_timer4_mpu_irqs,
- .main_clk = "gpt4_fck",
+/* I2C1 */
+static struct omap_hwmod omap2420_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = omap2_i2c1_sdma_reqs,
+ .main_clk = "i2c1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT4_SHIFT,
.module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
- },
- },
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2420_timer4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
- .class = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer5 */
-static struct omap_hwmod omap2420_timer5_hwmod;
-
-/* l4_core -> timer5 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer5_hwmod,
- .clk = "gpt5_ick",
- .addr = omap2xxx_timer5_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer5 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
- &omap2420_l4_core__timer5,
-};
-
-/* timer5 hwmod */
-static struct omap_hwmod omap2420_timer5_hwmod = {
- .name = "timer5",
- .mpu_irqs = omap2_timer5_mpu_irqs,
- .main_clk = "gpt5_fck",
- .prcm = {
- .omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT5_SHIFT,
- .module_offs = CORE_MOD,
+ .module_bit = OMAP2420_EN_I2C1_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+ .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2420_timer5_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
- .class = &omap2xxx_timer_hwmod_class,
-};
-
-
-/* timer6 */
-static struct omap_hwmod omap2420_timer6_hwmod;
-
-/* l4_core -> timer6 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer6_hwmod,
- .clk = "gpt6_ick",
- .addr = omap2xxx_timer6_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer6 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
- &omap2420_l4_core__timer6,
+ .class = &i2c_class,
+ .dev_attr = &i2c_dev_attr,
+ .flags = HWMOD_16BIT_REG,
};
-/* timer6 hwmod */
-static struct omap_hwmod omap2420_timer6_hwmod = {
- .name = "timer6",
- .mpu_irqs = omap2_timer6_mpu_irqs,
- .main_clk = "gpt6_fck",
+/* I2C2 */
+static struct omap_hwmod omap2420_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = omap2_i2c2_sdma_reqs,
+ .main_clk = "i2c2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT6_SHIFT,
.module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
- },
- },
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2420_timer6_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
- .class = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer7 */
-static struct omap_hwmod omap2420_timer7_hwmod;
-
-/* l4_core -> timer7 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer7_hwmod,
- .clk = "gpt7_ick",
- .addr = omap2xxx_timer7_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer7 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
- &omap2420_l4_core__timer7,
-};
-
-/* timer7 hwmod */
-static struct omap_hwmod omap2420_timer7_hwmod = {
- .name = "timer7",
- .mpu_irqs = omap2_timer7_mpu_irqs,
- .main_clk = "gpt7_fck",
- .prcm = {
- .omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT7_SHIFT,
- .module_offs = CORE_MOD,
+ .module_bit = OMAP2420_EN_I2C2_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+ .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2420_timer7_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
- .class = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer8 */
-static struct omap_hwmod omap2420_timer8_hwmod;
-
-/* l4_core -> timer8 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer8_hwmod,
- .clk = "gpt8_ick",
- .addr = omap2xxx_timer8_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer8 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
- &omap2420_l4_core__timer8,
+ .class = &i2c_class,
+ .dev_attr = &i2c_dev_attr,
+ .flags = HWMOD_16BIT_REG,
};
-/* timer8 hwmod */
-static struct omap_hwmod omap2420_timer8_hwmod = {
- .name = "timer8",
- .mpu_irqs = omap2_timer8_mpu_irqs,
- .main_clk = "gpt8_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT8_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
- },
- },
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2420_timer8_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
- .class = &omap2xxx_timer_hwmod_class,
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+ IS_CSSA_32 | IS_CDSA_32,
+ .lch_count = 32,
};
-/* timer9 */
-static struct omap_hwmod omap2420_timer9_hwmod;
-
-/* l4_core -> timer9 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer9_hwmod,
- .clk = "gpt9_ick",
- .addr = omap2xxx_timer9_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod omap2420_dma_system_hwmod = {
+ .name = "dma",
+ .class = &omap2xxx_dma_hwmod_class,
+ .mpu_irqs = omap2_dma_system_irqs,
+ .main_clk = "core_l3_ck",
+ .dev_attr = &dma_dev_attr,
+ .flags = HWMOD_NO_IDLEST,
};
-/* timer9 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
- &omap2420_l4_core__timer9,
+/* mailbox */
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+ { .name = "dsp", .irq = 26 },
+ { .name = "iva", .irq = 34 },
+ { .irq = -1 }
};
-/* timer9 hwmod */
-static struct omap_hwmod omap2420_timer9_hwmod = {
- .name = "timer9",
- .mpu_irqs = omap2_timer9_mpu_irqs,
- .main_clk = "gpt9_fck",
+static struct omap_hwmod omap2420_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap2xxx_mailbox_hwmod_class,
+ .mpu_irqs = omap2420_mailbox_irqs,
+ .main_clk = "mailboxes_ick",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap2420_timer9_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
- .class = &omap2xxx_timer_hwmod_class,
};
-/* timer10 */
-static struct omap_hwmod omap2420_timer10_hwmod;
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
-/* l4_core -> timer10 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer10_hwmod,
- .clk = "gpt10_ick",
- .addr = omap2_timer10_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
+ .name = "mcbsp",
};
-/* timer10 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
- &omap2420_l4_core__timer10,
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
+ { .name = "tx", .irq = 59 },
+ { .name = "rx", .irq = 60 },
+ { .irq = -1 }
};
-/* timer10 hwmod */
-static struct omap_hwmod omap2420_timer10_hwmod = {
- .name = "timer10",
- .mpu_irqs = omap2_timer10_mpu_irqs,
- .main_clk = "gpt10_fck",
+static struct omap_hwmod omap2420_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap2420_mcbsp_hwmod_class,
+ .mpu_irqs = omap2420_mcbsp1_irqs,
+ .sdma_reqs = omap2_mcbsp1_sdma_reqs,
+ .main_clk = "mcbsp1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+ .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap2420_timer10_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
- .class = &omap2xxx_timer_hwmod_class,
};
-/* timer11 */
-static struct omap_hwmod omap2420_timer11_hwmod;
-
-/* l4_core -> timer11 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer11_hwmod,
- .clk = "gpt11_ick",
- .addr = omap2_timer11_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer11 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
- &omap2420_l4_core__timer11,
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
+ { .name = "tx", .irq = 62 },
+ { .name = "rx", .irq = 63 },
+ { .irq = -1 }
};
-/* timer11 hwmod */
-static struct omap_hwmod omap2420_timer11_hwmod = {
- .name = "timer11",
- .mpu_irqs = omap2_timer11_mpu_irqs,
- .main_clk = "gpt11_fck",
+static struct omap_hwmod omap2420_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap2420_mcbsp_hwmod_class,
+ .mpu_irqs = omap2420_mcbsp2_irqs,
+ .sdma_reqs = omap2_mcbsp2_sdma_reqs,
+ .main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+ .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap2420_timer11_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
- .class = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer12 */
-static struct omap_hwmod omap2420_timer12_hwmod;
-
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_timer12_hwmod,
- .clk = "gpt12_ick",
- .addr = omap2xxx_timer12_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* timer12 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
- &omap2420_l4_core__timer12,
+static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
+ .rev_offs = 0x3c,
+ .sysc_offs = 0x64,
+ .syss_offs = 0x68,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* timer12 hwmod */
-static struct omap_hwmod omap2420_timer12_hwmod = {
- .name = "timer12",
- .mpu_irqs = omap2xxx_timer12_mpu_irqs,
- .main_clk = "gpt12_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT12_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
- },
- },
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap2420_timer12_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
- .class = &omap2xxx_timer_hwmod_class,
+static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
+ .name = "msdi",
+ .sysc = &omap2420_msdi_sysc,
+ .reset = &omap_msdi_reset,
};
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
- {
- .pa_start = 0x48022000,
- .pa_end = 0x4802207f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
- .master = &omap2420_l4_wkup_hwmod,
- .slave = &omap2420_wd_timer2_hwmod,
- .clk = "mpu_wdt_ick",
- .addr = omap2420_wd_timer2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* msdi1 */
+static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
+ { .irq = 83 },
+ { .irq = -1 }
};
-/* wd_timer2 */
-static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
- &omap2420_l4_wkup__wd_timer2,
+static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
+ { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
+ { .dma_req = -1 }
};
-static struct omap_hwmod omap2420_wd_timer2_hwmod = {
- .name = "wd_timer2",
- .class = &omap2xxx_wd_timer_hwmod_class,
- .main_clk = "mpu_wdt_fck",
+static struct omap_hwmod omap2420_msdi1_hwmod = {
+ .name = "msdi1",
+ .class = &omap2420_msdi_hwmod_class,
+ .mpu_irqs = omap2420_msdi1_irqs,
+ .sdma_reqs = omap2420_msdi1_sdma_reqs,
+ .main_clk = "mmc_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
- },
- },
- .slaves = omap2420_wd_timer2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
-};
-
-/* UART1 */
-
-static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
- &omap2_l4_core__uart1,
-};
-
-static struct omap_hwmod omap2420_uart1_hwmod = {
- .name = "uart1",
- .mpu_irqs = omap2_uart1_mpu_irqs,
- .sdma_reqs = omap2_uart1_sdma_reqs,
- .main_clk = "uart1_fck",
- .prcm = {
- .omap2 = {
+ .module_bit = OMAP2420_EN_MMC_SHIFT,
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_UART1_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+ .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
},
},
- .slaves = omap2420_uart1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
- .class = &omap2_uart_class,
-};
-
-/* UART2 */
-
-static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
- &omap2_l4_core__uart2,
+ .flags = HWMOD_16BIT_REG,
};
-static struct omap_hwmod omap2420_uart2_hwmod = {
- .name = "uart2",
- .mpu_irqs = omap2_uart2_mpu_irqs,
- .sdma_reqs = omap2_uart2_sdma_reqs,
- .main_clk = "uart2_fck",
+/* HDQ1W/1-wire */
+static struct omap_hwmod omap2420_hdq1w_hwmod = {
+ .name = "hdq1w",
+ .mpu_irqs = omap2_hdq1w_mpu_irqs,
+ .main_clk = "hdq_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_UART2_SHIFT,
+ .module_bit = OMAP24XX_EN_HDQ_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+ .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
},
},
- .slaves = omap2420_uart2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
- .class = &omap2_uart_class,
+ .class = &omap2_hdq1w_class,
};
-/* UART3 */
-
-static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
- &omap2_l4_core__uart3,
-};
-
-static struct omap_hwmod omap2420_uart3_hwmod = {
- .name = "uart3",
- .mpu_irqs = omap2_uart3_mpu_irqs,
- .sdma_reqs = omap2_uart3_sdma_reqs,
- .main_clk = "uart3_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 2,
- .module_bit = OMAP24XX_EN_UART3_SHIFT,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
- },
- },
- .slaves = omap2420_uart3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
- .class = &omap2_uart_class,
-};
-
-/* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
- &omap2420_dss__l3,
-};
+/*
+ * interfaces
+ */
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_dss_core_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_addrs,
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
- .flags = OMAP_FIREWALL_L4,
- }
- },
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2420_i2c1_hwmod,
+ .clk = "i2c1_ick",
+ .addr = omap2_i2c1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
- &omap2420_l4_core__dss,
-};
-
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- /*
- * The DSS HW needs all DSS clocks enabled during reset. The dss_core
- * driver does not use these clocks.
- */
- { .role = "tv_clk", .clk = "dss_54m_fck" },
- { .role = "sys_clk", .clk = "dss2_fck" },
-};
-
-static struct omap_hwmod omap2420_dss_core_hwmod = {
- .name = "dss_core",
- .class = &omap2_dss_hwmod_class,
- .main_clk = "dss1_fck", /* instead of dss_fck */
- .sdma_reqs = omap2xxx_dss_sdma_chs,
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
- },
- },
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
- .slaves = omap2420_dss_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
- .masters = omap2420_dss_masters,
- .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
- .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-};
-
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_dss_dispc_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_dispc_addrs,
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
- .flags = OMAP_FIREWALL_L4,
- }
- },
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2420_i2c2_hwmod,
+ .clk = "i2c2_ick",
+ .addr = omap2_i2c2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
- &omap2420_l4_core__dss_dispc,
-};
-
-static struct omap_hwmod omap2420_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &omap2_dispc_hwmod_class,
- .mpu_irqs = omap2_dispc_irqs,
- .main_clk = "dss1_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
- },
- },
- .slaves = omap2420_dss_dispc_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
- .flags = HWMOD_NO_IDLEST,
- .dev_attr = &omap2_3_dss_dispc_dev_attr
-};
-
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_dss_rfbi_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_rfbi_addrs,
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
- .flags = OMAP_FIREWALL_L4,
- }
- },
+/* IVA <- L3 interface */
+static struct omap_hwmod_ocp_if omap2420_l3__iva = {
+ .master = &omap2xxx_l3_main_hwmod,
+ .slave = &omap2420_iva_hwmod,
+ .clk = "core_l3_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
- &omap2420_l4_core__dss_rfbi,
-};
-
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
- { .role = "ick", .clk = "dss_ick" },
-};
-
-static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap2_rfbi_hwmod_class,
- .main_clk = "dss1_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
- .module_offs = CORE_MOD,
- },
- },
- .opt_clks = dss_rfbi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
- .slaves = omap2420_dss_rfbi_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
- .master = &omap2420_l4_core_hwmod,
- .slave = &omap2420_dss_venc_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_venc_addrs,
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
- .flags = OMAP_FIREWALL_L4,
- }
- },
+/* DSP <- L3 interface */
+static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
+ .master = &omap2xxx_l3_main_hwmod,
+ .slave = &omap2420_dsp_hwmod,
+ .clk = "dsp_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
- &omap2420_l4_core__dss_venc,
-};
-
-static struct omap_hwmod omap2420_dss_venc_hwmod = {
- .name = "dss_venc",
- .class = &omap2_venc_hwmod_class,
- .main_clk = "dss_54m_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
- .module_offs = CORE_MOD,
- },
- },
- .slaves = omap2420_dss_venc_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* I2C common */
-static struct omap_hwmod_class_sysconfig i2c_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x20,
- .syss_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class i2c_class = {
- .name = "i2c",
- .sysc = &i2c_sysc,
- .rev = OMAP_I2C_IP_VERSION_1,
- .reset = &omap_i2c_reset,
-};
-
-static struct omap_i2c_dev_attr i2c_dev_attr = {
- .flags = OMAP_I2C_FLAG_NO_FIFO |
- OMAP_I2C_FLAG_SIMPLE_CLOCK |
- OMAP_I2C_FLAG_16BIT_DATA_REG |
- OMAP_I2C_FLAG_BUS_SHIFT_2,
-};
-
-/* I2C1 */
-
-static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
- &omap2420_l4_core__i2c1,
-};
-
-static struct omap_hwmod omap2420_i2c1_hwmod = {
- .name = "i2c1",
- .mpu_irqs = omap2_i2c1_mpu_irqs,
- .sdma_reqs = omap2_i2c1_sdma_reqs,
- .main_clk = "i2c1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP2420_EN_I2C1_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
- },
- },
- .slaves = omap2420_i2c1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
- .class = &i2c_class,
- .dev_attr = &i2c_dev_attr,
- .flags = HWMOD_16BIT_REG,
-};
-
-/* I2C2 */
+static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
+ {
+ .pa_start = 0x48028000,
+ .pa_end = 0x48028000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
-static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
- &omap2420_l4_core__i2c2,
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_timer1_hwmod,
+ .clk = "gpt1_ick",
+ .addr = omap2420_timer1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap2420_i2c2_hwmod = {
- .name = "i2c2",
- .mpu_irqs = omap2_i2c2_mpu_irqs,
- .sdma_reqs = omap2_i2c2_sdma_reqs,
- .main_clk = "i2c2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP2420_EN_I2C2_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
- },
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
+ {
+ .pa_start = 0x48022000,
+ .pa_end = 0x4802207f,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap2420_i2c2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
- .class = &i2c_class,
- .dev_attr = &i2c_dev_attr,
- .flags = HWMOD_16BIT_REG,
+ { }
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_wd_timer2_hwmod,
+ .clk = "mpu_wdt_ick",
+ .addr = omap2420_wd_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> gpio1 */
};
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
- .master = &omap2420_l4_wkup_hwmod,
- .slave = &omap2420_gpio1_hwmod,
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_gpio1_hwmod,
.clk = "gpios_ick",
.addr = omap2420_gpio1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
- .master = &omap2420_l4_wkup_hwmod,
- .slave = &omap2420_gpio2_hwmod,
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_gpio2_hwmod,
.clk = "gpios_ick",
.addr = omap2420_gpio2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
- .master = &omap2420_l4_wkup_hwmod,
- .slave = &omap2420_gpio3_hwmod,
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_gpio3_hwmod,
.clk = "gpios_ick",
.addr = omap2420_gpio3_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
- .master = &omap2420_l4_wkup_hwmod,
- .slave = &omap2420_gpio4_hwmod,
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_gpio4_hwmod,
.clk = "gpios_ick",
.addr = omap2420_gpio4_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
- .bank_width = 32,
- .dbck_flag = false,
-};
-
-/* gpio1 */
-static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
- &omap2420_l4_wkup__gpio1,
-};
-
-static struct omap_hwmod omap2420_gpio1_hwmod = {
- .name = "gpio1",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio1_irqs,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .slaves = omap2420_gpio1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
- .class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
-
-/* gpio2 */
-static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
- &omap2420_l4_wkup__gpio2,
-};
-
-static struct omap_hwmod omap2420_gpio2_hwmod = {
- .name = "gpio2",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio2_irqs,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .slaves = omap2420_gpio2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
- .class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
-
-/* gpio3 */
-static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
- &omap2420_l4_wkup__gpio3,
-};
-
-static struct omap_hwmod omap2420_gpio3_hwmod = {
- .name = "gpio3",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio3_irqs,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .slaves = omap2420_gpio3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
- .class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
-
-/* gpio4 */
-static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
- &omap2420_l4_wkup__gpio4,
-};
-
-static struct omap_hwmod omap2420_gpio4_hwmod = {
- .name = "gpio4",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio4_irqs,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .slaves = omap2420_gpio4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
- .class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
-
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32,
- .lch_count = 32,
-};
-
/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
.master = &omap2420_dma_system_hwmod,
- .slave = &omap2420_l3_main_hwmod,
+ .slave = &omap2xxx_l3_main_hwmod,
.clk = "core_l3_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
- &omap2420_dma_system__l3,
-};
-
/* l4_core -> dma_system */
static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
- .master = &omap2420_l4_core_hwmod,
+ .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2420_dma_system_hwmod,
.clk = "sdma_ick",
.addr = omap2_dma_system_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
- &omap2420_l4_core__dma_system,
-};
-
-static struct omap_hwmod omap2420_dma_system_hwmod = {
- .name = "dma",
- .class = &omap2xxx_dma_hwmod_class,
- .mpu_irqs = omap2_dma_system_irqs,
- .main_clk = "core_l3_ck",
- .slaves = omap2420_dma_system_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
- .masters = omap2420_dma_system_masters,
- .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
- .dev_attr = &dma_dev_attr,
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* mailbox */
-static struct omap_hwmod omap2420_mailbox_hwmod;
-static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
- { .name = "dsp", .irq = 26 },
- { .name = "iva", .irq = 34 },
- { .irq = -1 }
-};
-
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
- .master = &omap2420_l4_core_hwmod,
+ .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2420_mailbox_hwmod,
.addr = omap2_mailbox_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
- &omap2420_l4_core__mailbox,
-};
-
-static struct omap_hwmod omap2420_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap2xxx_mailbox_hwmod_class,
- .mpu_irqs = omap2420_mailbox_irqs,
- .main_clk = "mailboxes_ick",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
- },
- },
- .slaves = omap2420_mailbox_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
-};
-
-/* mcspi1 */
-static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
- &omap2420_l4_core__mcspi1,
-};
-
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
- .num_chipselect = 4,
-};
-
-static struct omap_hwmod omap2420_mcspi1_hwmod = {
- .name = "mcspi1_hwmod",
- .mpu_irqs = omap2_mcspi1_mpu_irqs,
- .sdma_reqs = omap2_mcspi1_sdma_reqs,
- .main_clk = "mcspi1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
- },
- },
- .slaves = omap2420_mcspi1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
- .class = &omap2xxx_mcspi_class,
- .dev_attr = &omap_mcspi1_dev_attr,
-};
-
-/* mcspi2 */
-static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
- &omap2420_l4_core__mcspi2,
-};
-
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
- .num_chipselect = 2,
-};
-
-static struct omap_hwmod omap2420_mcspi2_hwmod = {
- .name = "mcspi2_hwmod",
- .mpu_irqs = omap2_mcspi2_mpu_irqs,
- .sdma_reqs = omap2_mcspi2_sdma_reqs,
- .main_clk = "mcspi2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
- },
- },
- .slaves = omap2420_mcspi2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
- .class = &omap2xxx_mcspi_class,
- .dev_attr = &omap_mcspi2_dev_attr,
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
- .name = "mcbsp",
-};
-
-/* mcbsp1 */
-static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
- { .name = "tx", .irq = 59 },
- { .name = "rx", .irq = 60 },
- { .irq = -1 }
-};
-
/* l4_core -> mcbsp1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
- .master = &omap2420_l4_core_hwmod,
+ .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2420_mcbsp1_hwmod,
.clk = "mcbsp1_ick",
.addr = omap2_mcbsp1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
- &omap2420_l4_core__mcbsp1,
-};
-
-static struct omap_hwmod omap2420_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap2420_mcbsp_hwmod_class,
- .mpu_irqs = omap2420_mcbsp1_irqs,
- .sdma_reqs = omap2_mcbsp1_sdma_reqs,
- .main_clk = "mcbsp1_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
- },
- },
- .slaves = omap2420_mcbsp1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
-};
-
-/* mcbsp2 */
-static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
- { .name = "tx", .irq = 62 },
- { .name = "rx", .irq = 63 },
- { .irq = -1 }
-};
-
/* l4_core -> mcbsp2 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
- .master = &omap2420_l4_core_hwmod,
+ .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2420_mcbsp2_hwmod,
.clk = "mcbsp2_ick",
.addr = omap2xxx_mcbsp2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
- &omap2420_l4_core__mcbsp2,
-};
-
-static struct omap_hwmod omap2420_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap2420_mcbsp_hwmod_class,
- .mpu_irqs = omap2420_mcbsp2_irqs,
- .sdma_reqs = omap2_mcbsp2_sdma_reqs,
- .main_clk = "mcbsp2_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
- },
+static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
+ {
+ .pa_start = 0x4809c000,
+ .pa_end = 0x4809c000 + SZ_128 - 1,
+ .flags = ADDR_TYPE_RT,
},
- .slaves = omap2420_mcbsp2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
+ { }
};
-static __initdata struct omap_hwmod *omap2420_hwmods[] = {
- &omap2420_l3_main_hwmod,
- &omap2420_l4_core_hwmod,
- &omap2420_l4_wkup_hwmod,
- &omap2420_mpu_hwmod,
- &omap2420_iva_hwmod,
-
- &omap2420_timer1_hwmod,
- &omap2420_timer2_hwmod,
- &omap2420_timer3_hwmod,
- &omap2420_timer4_hwmod,
- &omap2420_timer5_hwmod,
- &omap2420_timer6_hwmod,
- &omap2420_timer7_hwmod,
- &omap2420_timer8_hwmod,
- &omap2420_timer9_hwmod,
- &omap2420_timer10_hwmod,
- &omap2420_timer11_hwmod,
- &omap2420_timer12_hwmod,
-
- &omap2420_wd_timer2_hwmod,
- &omap2420_uart1_hwmod,
- &omap2420_uart2_hwmod,
- &omap2420_uart3_hwmod,
- /* dss class */
- &omap2420_dss_core_hwmod,
- &omap2420_dss_dispc_hwmod,
- &omap2420_dss_rfbi_hwmod,
- &omap2420_dss_venc_hwmod,
- /* i2c class */
- &omap2420_i2c1_hwmod,
- &omap2420_i2c2_hwmod,
+/* l4_core -> msdi1 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2420_msdi1_hwmod,
+ .clk = "mmc_ick",
+ .addr = omap2420_msdi1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
- /* gpio class */
- &omap2420_gpio1_hwmod,
- &omap2420_gpio2_hwmod,
- &omap2420_gpio3_hwmod,
- &omap2420_gpio4_hwmod,
+/* l4_core -> hdq1w interface */
+static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2420_hdq1w_hwmod,
+ .clk = "hdq_ick",
+ .addr = omap2_hdq1w_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
+};
- /* dma_system class*/
- &omap2420_dma_system_hwmod,
- /* mailbox class */
- &omap2420_mailbox_hwmod,
+/* l4_wkup -> 32ksync_counter */
+static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
+ {
+ .pa_start = 0x48004000,
+ .pa_end = 0x4800401f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
- /* mcbsp class */
- &omap2420_mcbsp1_hwmod,
- &omap2420_mcbsp2_hwmod,
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_counter_32k_hwmod,
+ .clk = "sync_32k_ick",
+ .addr = omap2420_counter_32k_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
- /* mcspi class */
- &omap2420_mcspi1_hwmod,
- &omap2420_mcspi2_hwmod,
+static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
+ &omap2xxx_l3_main__l4_core,
+ &omap2xxx_mpu__l3_main,
+ &omap2xxx_dss__l3,
+ &omap2xxx_l4_core__mcspi1,
+ &omap2xxx_l4_core__mcspi2,
+ &omap2xxx_l4_core__l4_wkup,
+ &omap2_l4_core__uart1,
+ &omap2_l4_core__uart2,
+ &omap2_l4_core__uart3,
+ &omap2420_l4_core__i2c1,
+ &omap2420_l4_core__i2c2,
+ &omap2420_l3__iva,
+ &omap2420_l3__dsp,
+ &omap2420_l4_wkup__timer1,
+ &omap2xxx_l4_core__timer2,
+ &omap2xxx_l4_core__timer3,
+ &omap2xxx_l4_core__timer4,
+ &omap2xxx_l4_core__timer5,
+ &omap2xxx_l4_core__timer6,
+ &omap2xxx_l4_core__timer7,
+ &omap2xxx_l4_core__timer8,
+ &omap2xxx_l4_core__timer9,
+ &omap2xxx_l4_core__timer10,
+ &omap2xxx_l4_core__timer11,
+ &omap2xxx_l4_core__timer12,
+ &omap2420_l4_wkup__wd_timer2,
+ &omap2xxx_l4_core__dss,
+ &omap2xxx_l4_core__dss_dispc,
+ &omap2xxx_l4_core__dss_rfbi,
+ &omap2xxx_l4_core__dss_venc,
+ &omap2420_l4_wkup__gpio1,
+ &omap2420_l4_wkup__gpio2,
+ &omap2420_l4_wkup__gpio3,
+ &omap2420_l4_wkup__gpio4,
+ &omap2420_dma_system__l3,
+ &omap2420_l4_core__dma_system,
+ &omap2420_l4_core__mailbox,
+ &omap2420_l4_core__mcbsp1,
+ &omap2420_l4_core__mcbsp2,
+ &omap2420_l4_core__msdi1,
+ &omap2420_l4_core__hdq1w,
+ &omap2420_l4_wkup__counter_32k,
NULL,
};
int __init omap2420_hwmod_init(void)
{
- return omap_hwmod_register(omap2420_hwmods);
+ return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
}
* omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
*
* Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
/*
* OMAP2430 hardware module integration data
*
- * ALl of the data in this section should be autogeneratable from the
+ * All of the data in this section should be autogeneratable from the
* TI hardware database or other technical documentation. Data that
* is driver-specific or driver-kernel integration-specific belongs
* elsewhere.
*/
-static struct omap_hwmod omap2430_mpu_hwmod;
-static struct omap_hwmod omap2430_iva_hwmod;
-static struct omap_hwmod omap2430_l3_main_hwmod;
-static struct omap_hwmod omap2430_l4_core_hwmod;
-static struct omap_hwmod omap2430_dss_core_hwmod;
-static struct omap_hwmod omap2430_dss_dispc_hwmod;
-static struct omap_hwmod omap2430_dss_rfbi_hwmod;
-static struct omap_hwmod omap2430_dss_venc_hwmod;
-static struct omap_hwmod omap2430_wd_timer2_hwmod;
-static struct omap_hwmod omap2430_gpio1_hwmod;
-static struct omap_hwmod omap2430_gpio2_hwmod;
-static struct omap_hwmod omap2430_gpio3_hwmod;
-static struct omap_hwmod omap2430_gpio4_hwmod;
-static struct omap_hwmod omap2430_gpio5_hwmod;
-static struct omap_hwmod omap2430_dma_system_hwmod;
-static struct omap_hwmod omap2430_mcbsp1_hwmod;
-static struct omap_hwmod omap2430_mcbsp2_hwmod;
-static struct omap_hwmod omap2430_mcbsp3_hwmod;
-static struct omap_hwmod omap2430_mcbsp4_hwmod;
-static struct omap_hwmod omap2430_mcbsp5_hwmod;
-static struct omap_hwmod omap2430_mcspi1_hwmod;
-static struct omap_hwmod omap2430_mcspi2_hwmod;
-static struct omap_hwmod omap2430_mcspi3_hwmod;
-static struct omap_hwmod omap2430_mmc1_hwmod;
-static struct omap_hwmod omap2430_mmc2_hwmod;
-
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
- .master = &omap2430_l3_main_hwmod,
- .slave = &omap2430_l4_core_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
+/*
+ * IP blocks
+ */
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
- .master = &omap2430_mpu_hwmod,
- .slave = &omap2430_l3_main_hwmod,
- .user = OCP_USER_MPU,
+/* IVA2 (IVA2) */
+static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
+ { .name = "logic", .rst_shift = 0 },
+ { .name = "mmu", .rst_shift = 1 },
};
-/* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
- &omap2430_mpu__l3_main,
+static struct omap_hwmod omap2430_iva_hwmod = {
+ .name = "iva",
+ .class = &iva_hwmod_class,
+ .clkdm_name = "dsp_clkdm",
+ .rst_lines = omap2430_iva_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
+ .main_clk = "dsp_fck",
};
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
- .master = &omap2430_dss_core_hwmod,
- .slave = &omap2430_l3_main_hwmod,
- .fw = {
- .omap2 = {
- .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
- .flags = OMAP_FIREWALL_L3,
- }
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x20,
+ .syss_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
- &omap2430_l3_main__l4_core,
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_1,
+ .reset = &omap_i2c_reset,
};
-/* L3 */
-static struct omap_hwmod omap2430_l3_main_hwmod = {
- .name = "l3_main",
- .class = &l3_hwmod_class,
- .masters = omap2430_l3_main_masters,
- .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters),
- .slaves = omap2430_l3_main_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves),
- .flags = HWMOD_NO_IDLEST,
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+ OMAP_I2C_FLAG_BUS_SHIFT_2 |
+ OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
};
-static struct omap_hwmod omap2430_l4_wkup_hwmod;
-static struct omap_hwmod omap2430_uart1_hwmod;
-static struct omap_hwmod omap2430_uart2_hwmod;
-static struct omap_hwmod omap2430_uart3_hwmod;
-static struct omap_hwmod omap2430_i2c1_hwmod;
-static struct omap_hwmod omap2430_i2c2_hwmod;
-
-static struct omap_hwmod omap2430_usbhsotg_hwmod;
-
-/* l3_core -> usbhsotg interface */
-static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
- .master = &omap2430_usbhsotg_hwmod,
- .slave = &omap2430_l3_main_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU,
+/* I2C1 */
+static struct omap_hwmod omap2430_i2c1_hwmod = {
+ .name = "i2c1",
+ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = omap2_i2c1_sdma_reqs,
+ .main_clk = "i2chs1_fck",
+ .prcm = {
+ .omap2 = {
+ /*
+ * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
+ * I2CHS IP's do not follow the usual pattern.
+ * prcm_reg_id alone cannot be used to program
+ * the iclk and fclk. Needs to be handled using
+ * additional flags when clk handling is moved
+ * to hwmod framework.
+ */
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
+ },
+ },
+ .class = &i2c_class,
+ .dev_attr = &i2c_dev_attr,
};
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_i2c1_hwmod,
- .clk = "i2c1_ick",
- .addr = omap2_i2c1_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* I2C2 */
+static struct omap_hwmod omap2430_i2c2_hwmod = {
+ .name = "i2c2",
+ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = omap2_i2c2_sdma_reqs,
+ .main_clk = "i2chs2_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
+ },
+ },
+ .class = &i2c_class,
+ .dev_attr = &i2c_dev_attr,
};
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_i2c2_hwmod,
- .clk = "i2c2_ick",
- .addr = omap2_i2c2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* gpio5 */
+static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
+ { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
+ { .irq = -1 }
};
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_l4_wkup_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod omap2430_gpio5_hwmod = {
+ .name = "gpio5",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap243x_gpio5_irqs,
+ .main_clk = "gpio5_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 2,
+ .module_bit = OMAP2430_EN_GPIO5_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 2,
+ .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
+ },
+ },
+ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &omap2xxx_gpio_dev_attr,
};
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_uart1_hwmod,
- .clk = "uart1_ick",
- .addr = omap2xxx_uart1_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+ IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+ .lch_count = 32,
};
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_uart2_hwmod,
- .clk = "uart2_ick",
- .addr = omap2xxx_uart2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod omap2430_dma_system_hwmod = {
+ .name = "dma",
+ .class = &omap2xxx_dma_hwmod_class,
+ .mpu_irqs = omap2_dma_system_irqs,
+ .main_clk = "core_l3_ck",
+ .dev_attr = &dma_dev_attr,
+ .flags = HWMOD_NO_IDLEST,
};
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_uart3_hwmod,
- .clk = "uart3_ick",
- .addr = omap2xxx_uart3_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* mailbox */
+static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+ { .irq = 26 },
+ { .irq = -1 }
};
-/*
-* usbhsotg interface data
-*/
-static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
- {
- .pa_start = OMAP243X_HS_BASE,
- .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod omap2430_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap2xxx_mailbox_hwmod_class,
+ .mpu_irqs = omap2430_mailbox_irqs,
+ .main_clk = "mailboxes_ick",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+ },
},
- { }
};
-/* l4_core ->usbhsotg interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_usbhsotg_hwmod,
- .clk = "usb_l4_ick",
- .addr = omap2430_usbhsotg_addrs,
- .user = OCP_USER_MPU,
+/* mcspi3 */
+static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
+ { .irq = 91 },
+ { .irq = -1 }
};
-static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
- &omap2430_usbhsotg__l3,
+static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
+ { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
+ { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
+ { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
+ { .dma_req = -1 }
};
-static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
- &omap2430_l4_core__usbhsotg,
+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+ .num_chipselect = 2,
};
-/* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_mmc1_hwmod,
- .clk = "mmchs1_ick",
- .addr = omap2430_mmc1_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod omap2430_mcspi3_hwmod = {
+ .name = "mcspi3",
+ .mpu_irqs = omap2430_mcspi3_mpu_irqs,
+ .sdma_reqs = omap2430_mcspi3_sdma_reqs,
+ .main_clk = "mcspi3_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 2,
+ .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
+ .idlest_reg_id = 2,
+ .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
+ },
+ },
+ .class = &omap2xxx_mcspi_class,
+ .dev_attr = &omap_mcspi3_dev_attr,
};
-/* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_mmc2_hwmod,
- .clk = "mmchs2_ick",
- .addr = omap2430_mmc2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* usbhsotg */
+static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
+ .rev_offs = 0x0400,
+ .sysc_offs = 0x0404,
+ .syss_offs = 0x0408,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* Slave interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
- &omap2430_l3_main__l4_core,
+static struct omap_hwmod_class usbotg_class = {
+ .name = "usbotg",
+ .sysc = &omap2430_usbhsotg_sysc,
};
-/* Master interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
- &omap2430_l4_core__l4_wkup,
- &omap2430_l4_core__mmc1,
- &omap2430_l4_core__mmc2,
-};
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
-/* L4 CORE */
-static struct omap_hwmod omap2430_l4_core_hwmod = {
- .name = "l4_core",
- .class = &l4_hwmod_class,
- .masters = omap2430_l4_core_masters,
- .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
- .slaves = omap2430_l4_core_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
- .flags = HWMOD_NO_IDLEST,
+ { .name = "mc", .irq = 92 },
+ { .name = "dma", .irq = 93 },
+ { .irq = -1 }
};
-/* Slave interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
- &omap2430_l4_core__l4_wkup,
- &omap2_l4_core__uart1,
- &omap2_l4_core__uart2,
- &omap2_l4_core__uart3,
+static struct omap_hwmod omap2430_usbhsotg_hwmod = {
+ .name = "usb_otg_hs",
+ .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
+ .main_clk = "usbhs_ick",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP2430_EN_USBHS_MASK,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
+ },
+ },
+ .class = &usbotg_class,
+ /*
+ * Erratum ID: i479 idle_req / idle_ack mechanism potentially
+ * broken when autoidle is enabled
+ * workaround is to disable the autoidle bit at module level.
+ */
+ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
+ | HWMOD_SWSUP_MSTANDBY,
};
-/* Master interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
-};
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_mcspi1_hwmod,
- .clk = "mcspi1_ick",
- .addr = omap2_mcspi1_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
+ .rev_offs = 0x007C,
+ .sysc_offs = 0x008C,
+ .sysc_flags = (SYSC_HAS_SOFTRESET),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_mcspi2_hwmod,
- .clk = "mcspi2_ick",
- .addr = omap2_mcspi2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi3 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_mcspi3_hwmod,
- .clk = "mcspi3_ick",
- .addr = omap2430_mcspi3_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 WKUP */
-static struct omap_hwmod omap2430_l4_wkup_hwmod = {
- .name = "l4_wkup",
- .class = &l4_hwmod_class,
- .masters = omap2430_l4_wkup_masters,
- .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
- .slaves = omap2430_l4_wkup_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* Master interfaces on the MPU device */
-static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
- &omap2430_mpu__l3_main,
-};
-
-/* MPU */
-static struct omap_hwmod omap2430_mpu_hwmod = {
- .name = "mpu",
- .class = &mpu_hwmod_class,
- .main_clk = "mpu_ck",
- .masters = omap2430_mpu_masters,
- .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
-};
-
-/*
- * IVA2_1 interface data
- */
-
-/* IVA2 <- L3 interface */
-static struct omap_hwmod_ocp_if omap2430_l3__iva = {
- .master = &omap2430_l3_main_hwmod,
- .slave = &omap2430_iva_hwmod,
- .clk = "dsp_fck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
- &omap2430_l3__iva,
-};
-
-/*
- * IVA2 (IVA2)
- */
-
-static struct omap_hwmod omap2430_iva_hwmod = {
- .name = "iva",
- .class = &iva_hwmod_class,
- .masters = omap2430_iva_masters,
- .masters_cnt = ARRAY_SIZE(omap2430_iva_masters),
-};
-
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_PWM,
-};
-
-/* timer1 */
-static struct omap_hwmod omap2430_timer1_hwmod;
-
-static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
- {
- .pa_start = 0x49018000,
- .pa_end = 0x49018000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
- .master = &omap2430_l4_wkup_hwmod,
- .slave = &omap2430_timer1_hwmod,
- .clk = "gpt1_ick",
- .addr = omap2430_timer1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
+ .name = "mcbsp",
+ .sysc = &omap2430_mcbsp_sysc,
+ .rev = MCBSP_CONFIG_TYPE2,
};
-/* timer1 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
- &omap2430_l4_wkup__timer1,
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
+ { .name = "tx", .irq = 59 },
+ { .name = "rx", .irq = 60 },
+ { .name = "ovr", .irq = 61 },
+ { .name = "common", .irq = 64 },
+ { .irq = -1 }
};
-/* timer1 hwmod */
-static struct omap_hwmod omap2430_timer1_hwmod = {
- .name = "timer1",
- .mpu_irqs = omap2_timer1_mpu_irqs,
- .main_clk = "gpt1_fck",
+static struct omap_hwmod omap2430_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp1_irqs,
+ .sdma_reqs = omap2_mcbsp1_sdma_reqs,
+ .main_clk = "mcbsp1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT1_SHIFT,
- .module_offs = WKUP_MOD,
+ .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+ .module_offs = CORE_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+ .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2430_timer1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
- .class = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer2 */
-static struct omap_hwmod omap2430_timer2_hwmod;
-
-/* l4_core -> timer2 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer2_hwmod,
- .clk = "gpt2_ick",
- .addr = omap2xxx_timer2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* timer2 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
- &omap2430_l4_core__timer2,
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
+ { .name = "tx", .irq = 62 },
+ { .name = "rx", .irq = 63 },
+ { .name = "common", .irq = 16 },
+ { .irq = -1 }
};
-/* timer2 hwmod */
-static struct omap_hwmod omap2430_timer2_hwmod = {
- .name = "timer2",
- .mpu_irqs = omap2_timer2_mpu_irqs,
- .main_clk = "gpt2_fck",
+static struct omap_hwmod omap2430_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp2_irqs,
+ .sdma_reqs = omap2_mcbsp2_sdma_reqs,
+ .main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+ .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2430_timer2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
- .class = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer3 */
-static struct omap_hwmod omap2430_timer3_hwmod;
-
-/* l4_core -> timer3 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer3_hwmod,
- .clk = "gpt3_ick",
- .addr = omap2xxx_timer3_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* timer3 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
- &omap2430_l4_core__timer3,
+/* mcbsp3 */
+static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
+ { .name = "tx", .irq = 89 },
+ { .name = "rx", .irq = 90 },
+ { .name = "common", .irq = 17 },
+ { .irq = -1 }
};
-/* timer3 hwmod */
-static struct omap_hwmod omap2430_timer3_hwmod = {
- .name = "timer3",
- .mpu_irqs = omap2_timer3_mpu_irqs,
- .main_clk = "gpt3_fck",
+static struct omap_hwmod omap2430_mcbsp3_hwmod = {
+ .name = "mcbsp3",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp3_irqs,
+ .sdma_reqs = omap2_mcbsp3_sdma_reqs,
+ .main_clk = "mcbsp3_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
.module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+ .idlest_reg_id = 2,
+ .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2430_timer3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
- .class = &omap2xxx_timer_hwmod_class,
};
-/* timer4 */
-static struct omap_hwmod omap2430_timer4_hwmod;
-
-/* l4_core -> timer4 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer4_hwmod,
- .clk = "gpt4_ick",
- .addr = omap2xxx_timer4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* mcbsp4 */
+static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
+ { .name = "tx", .irq = 54 },
+ { .name = "rx", .irq = 55 },
+ { .name = "common", .irq = 18 },
+ { .irq = -1 }
};
-/* timer4 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
- &omap2430_l4_core__timer4,
+static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
+ { .name = "rx", .dma_req = 20 },
+ { .name = "tx", .dma_req = 19 },
+ { .dma_req = -1 }
};
-/* timer4 hwmod */
-static struct omap_hwmod omap2430_timer4_hwmod = {
- .name = "timer4",
- .mpu_irqs = omap2_timer4_mpu_irqs,
- .main_clk = "gpt4_fck",
+static struct omap_hwmod omap2430_mcbsp4_hwmod = {
+ .name = "mcbsp4",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp4_irqs,
+ .sdma_reqs = omap2430_mcbsp4_sdma_chs,
+ .main_clk = "mcbsp4_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
.module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+ .idlest_reg_id = 2,
+ .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2430_timer4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
- .class = &omap2xxx_timer_hwmod_class,
};
-/* timer5 */
-static struct omap_hwmod omap2430_timer5_hwmod;
-
-/* l4_core -> timer5 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer5_hwmod,
- .clk = "gpt5_ick",
- .addr = omap2xxx_timer5_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* mcbsp5 */
+static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
+ { .name = "tx", .irq = 81 },
+ { .name = "rx", .irq = 82 },
+ { .name = "common", .irq = 19 },
+ { .irq = -1 }
};
-/* timer5 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
- &omap2430_l4_core__timer5,
+static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
+ { .name = "rx", .dma_req = 22 },
+ { .name = "tx", .dma_req = 21 },
+ { .dma_req = -1 }
};
-/* timer5 hwmod */
-static struct omap_hwmod omap2430_timer5_hwmod = {
- .name = "timer5",
- .mpu_irqs = omap2_timer5_mpu_irqs,
- .main_clk = "gpt5_fck",
+static struct omap_hwmod omap2430_mcbsp5_hwmod = {
+ .name = "mcbsp5",
+ .class = &omap2430_mcbsp_hwmod_class,
+ .mpu_irqs = omap2430_mcbsp5_irqs,
+ .sdma_reqs = omap2430_mcbsp5_sdma_chs,
+ .main_clk = "mcbsp5_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
.module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+ .idlest_reg_id = 2,
+ .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2430_timer5_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
- .class = &omap2xxx_timer_hwmod_class,
};
-/* timer6 */
-static struct omap_hwmod omap2430_timer6_hwmod;
-
-/* l4_core -> timer6 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer6_hwmod,
- .clk = "gpt6_ick",
- .addr = omap2xxx_timer6_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* MMC/SD/SDIO common */
+static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
+ .rev_offs = 0x1fc,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* timer6 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
- &omap2430_l4_core__timer6,
+static struct omap_hwmod_class omap2430_mmc_class = {
+ .name = "mmc",
+ .sysc = &omap2430_mmc_sysc,
};
-/* timer6 hwmod */
-static struct omap_hwmod omap2430_timer6_hwmod = {
- .name = "timer6",
- .mpu_irqs = omap2_timer6_mpu_irqs,
- .main_clk = "gpt6_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT6_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
- },
- },
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2430_timer6_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
- .class = &omap2xxx_timer_hwmod_class,
+/* MMC/SD/SDIO1 */
+static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
+ { .irq = 83 },
+ { .irq = -1 }
};
-/* timer7 */
-static struct omap_hwmod omap2430_timer7_hwmod;
+static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
+ { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
+ { .dma_req = -1 }
+};
-/* l4_core -> timer7 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer7_hwmod,
- .clk = "gpt7_ick",
- .addr = omap2xxx_timer7_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
+ { .role = "dbck", .clk = "mmchsdb1_fck" },
};
-/* timer7 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
- &omap2430_l4_core__timer7,
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};
-/* timer7 hwmod */
-static struct omap_hwmod omap2430_timer7_hwmod = {
- .name = "timer7",
- .mpu_irqs = omap2_timer7_mpu_irqs,
- .main_clk = "gpt7_fck",
+static struct omap_hwmod omap2430_mmc1_hwmod = {
+ .name = "mmc1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2430_mmc1_mpu_irqs,
+ .sdma_reqs = omap2430_mmc1_sdma_reqs,
+ .opt_clks = omap2430_mmc1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
+ .main_clk = "mmchs1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT7_SHIFT,
.module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+ .prcm_reg_id = 2,
+ .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
+ .idlest_reg_id = 2,
+ .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2430_timer7_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
- .class = &omap2xxx_timer_hwmod_class,
+ .dev_attr = &mmc1_dev_attr,
+ .class = &omap2430_mmc_class,
};
-/* timer8 */
-static struct omap_hwmod omap2430_timer8_hwmod;
+/* MMC/SD/SDIO2 */
+static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
+ { .irq = 86 },
+ { .irq = -1 }
+};
-/* l4_core -> timer8 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer8_hwmod,
- .clk = "gpt8_ick",
- .addr = omap2xxx_timer8_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
+ { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
+ { .dma_req = -1 }
};
-/* timer8 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
- &omap2430_l4_core__timer8,
+static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
+ { .role = "dbck", .clk = "mmchsdb2_fck" },
};
-/* timer8 hwmod */
-static struct omap_hwmod omap2430_timer8_hwmod = {
- .name = "timer8",
- .mpu_irqs = omap2_timer8_mpu_irqs,
- .main_clk = "gpt8_fck",
+static struct omap_hwmod omap2430_mmc2_hwmod = {
+ .name = "mmc2",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2430_mmc2_mpu_irqs,
+ .sdma_reqs = omap2430_mmc2_sdma_reqs,
+ .opt_clks = omap2430_mmc2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
+ .main_clk = "mmchs2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT8_SHIFT,
.module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+ .prcm_reg_id = 2,
+ .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
+ .idlest_reg_id = 2,
+ .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap2430_timer8_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
- .class = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer9 */
-static struct omap_hwmod omap2430_timer9_hwmod;
-
-/* l4_core -> timer9 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer9_hwmod,
- .clk = "gpt9_ick",
- .addr = omap2xxx_timer9_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer9 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
- &omap2430_l4_core__timer9,
+ .class = &omap2430_mmc_class,
};
-/* timer9 hwmod */
-static struct omap_hwmod omap2430_timer9_hwmod = {
- .name = "timer9",
- .mpu_irqs = omap2_timer9_mpu_irqs,
- .main_clk = "gpt9_fck",
+/* HDQ1W/1-wire */
+static struct omap_hwmod omap2430_hdq1w_hwmod = {
+ .name = "hdq1w",
+ .mpu_irqs = omap2_hdq1w_mpu_irqs,
+ .main_clk = "hdq_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT9_SHIFT,
.module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_HDQ_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+ .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap2430_timer9_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
- .class = &omap2xxx_timer_hwmod_class,
+ .class = &omap2_hdq1w_class,
};
-/* timer10 */
-static struct omap_hwmod omap2430_timer10_hwmod;
+/*
+ * interfaces
+ */
-/* l4_core -> timer10 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer10_hwmod,
- .clk = "gpt10_ick",
- .addr = omap2_timer10_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* L3 -> L4_CORE interface */
+/* l3_core -> usbhsotg interface */
+static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
+ .master = &omap2430_usbhsotg_hwmod,
+ .slave = &omap2xxx_l3_main_hwmod,
+ .clk = "core_l3_ck",
+ .user = OCP_USER_MPU,
};
-/* timer10 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
- &omap2430_l4_core__timer10,
-};
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_i2c1_hwmod,
+ .clk = "i2c1_ick",
+ .addr = omap2_i2c1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
-/* timer10 hwmod */
-static struct omap_hwmod omap2430_timer10_hwmod = {
- .name = "timer10",
- .mpu_irqs = omap2_timer10_mpu_irqs,
- .main_clk = "gpt10_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT10_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
- },
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_i2c2_hwmod,
+ .clk = "i2c2_ick",
+ .addr = omap2_i2c2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
+ {
+ .pa_start = OMAP243X_HS_BASE,
+ .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
},
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap2430_timer10_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
- .class = &omap2xxx_timer_hwmod_class,
+ { }
};
-/* timer11 */
-static struct omap_hwmod omap2430_timer11_hwmod;
+/* l4_core ->usbhsotg interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_usbhsotg_hwmod,
+ .clk = "usb_l4_ick",
+ .addr = omap2430_usbhsotg_addrs,
+ .user = OCP_USER_MPU,
+};
-/* l4_core -> timer11 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer11_hwmod,
- .clk = "gpt11_ick",
- .addr = omap2_timer11_addrs,
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_mmc1_hwmod,
+ .clk = "mmchs1_ick",
+ .addr = omap2430_mmc1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* timer11 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
- &omap2430_l4_core__timer11,
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_mmc2_hwmod,
+ .clk = "mmchs2_ick",
+ .addr = omap2430_mmc2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* timer11 hwmod */
-static struct omap_hwmod omap2430_timer11_hwmod = {
- .name = "timer11",
- .mpu_irqs = omap2_timer11_mpu_irqs,
- .main_clk = "gpt11_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT11_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
- },
- },
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap2430_timer11_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
- .class = &omap2xxx_timer_hwmod_class,
+/* l4 core -> mcspi3 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_mcspi3_hwmod,
+ .clk = "mcspi3_ick",
+ .addr = omap2430_mcspi3_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* timer12 */
-static struct omap_hwmod omap2430_timer12_hwmod;
-
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_timer12_hwmod,
- .clk = "gpt12_ick",
- .addr = omap2xxx_timer12_addrs,
+/* IVA2 <- L3 interface */
+static struct omap_hwmod_ocp_if omap2430_l3__iva = {
+ .master = &omap2xxx_l3_main_hwmod,
+ .slave = &omap2430_iva_hwmod,
+ .clk = "core_l3_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* timer12 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
- &omap2430_l4_core__timer12,
+static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+ {
+ .pa_start = 0x49018000,
+ .pa_end = 0x49018000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-/* timer12 hwmod */
-static struct omap_hwmod omap2430_timer12_hwmod = {
- .name = "timer12",
- .mpu_irqs = omap2xxx_timer12_mpu_irqs,
- .main_clk = "gpt12_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT12_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
- },
- },
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap2430_timer12_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
- .class = &omap2xxx_timer_hwmod_class,
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_timer1_hwmod,
+ .clk = "gpt1_ick",
+ .addr = omap2430_timer1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> wd_timer2 */
};
static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
- .master = &omap2430_l4_wkup_hwmod,
- .slave = &omap2430_wd_timer2_hwmod,
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_wd_timer2_hwmod,
.clk = "mpu_wdt_ick",
.addr = omap2430_wd_timer2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* wd_timer2 */
-static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
- &omap2430_l4_wkup__wd_timer2,
-};
-
-static struct omap_hwmod omap2430_wd_timer2_hwmod = {
- .name = "wd_timer2",
- .class = &omap2xxx_wd_timer_hwmod_class,
- .main_clk = "mpu_wdt_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
- },
- },
- .slaves = omap2430_wd_timer2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
-};
-
-/* UART1 */
-
-static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
- &omap2_l4_core__uart1,
-};
-
-static struct omap_hwmod omap2430_uart1_hwmod = {
- .name = "uart1",
- .mpu_irqs = omap2_uart1_mpu_irqs,
- .sdma_reqs = omap2_uart1_sdma_reqs,
- .main_clk = "uart1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_UART1_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
- },
- },
- .slaves = omap2430_uart1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
- .class = &omap2_uart_class,
-};
-
-/* UART2 */
-
-static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
- &omap2_l4_core__uart2,
-};
-
-static struct omap_hwmod omap2430_uart2_hwmod = {
- .name = "uart2",
- .mpu_irqs = omap2_uart2_mpu_irqs,
- .sdma_reqs = omap2_uart2_sdma_reqs,
- .main_clk = "uart2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_UART2_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
- },
- },
- .slaves = omap2430_uart2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
- .class = &omap2_uart_class,
-};
-
-/* UART3 */
-
-static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
- &omap2_l4_core__uart3,
-};
-
-static struct omap_hwmod omap2430_uart3_hwmod = {
- .name = "uart3",
- .mpu_irqs = omap2_uart3_mpu_irqs,
- .sdma_reqs = omap2_uart3_sdma_reqs,
- .main_clk = "uart3_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 2,
- .module_bit = OMAP24XX_EN_UART3_SHIFT,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
- },
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
+ {
+ .pa_start = 0x4900C000,
+ .pa_end = 0x4900C1ff,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap2430_uart3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
- .class = &omap2_uart_class,
-};
-
-/* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
- &omap2430_dss__l3,
+ { }
};
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_dss_core_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_addrs,
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_gpio1_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
- &omap2430_l4_core__dss,
-};
-
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- /*
- * The DSS HW needs all DSS clocks enabled during reset. The dss_core
- * driver does not use these clocks.
- */
- { .role = "tv_clk", .clk = "dss_54m_fck" },
- { .role = "sys_clk", .clk = "dss2_fck" },
-};
-
-static struct omap_hwmod omap2430_dss_core_hwmod = {
- .name = "dss_core",
- .class = &omap2_dss_hwmod_class,
- .main_clk = "dss1_fck", /* instead of dss_fck */
- .sdma_reqs = omap2xxx_dss_sdma_chs,
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
- },
+/* l4_wkup -> gpio2 */
+static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
+ {
+ .pa_start = 0x4900E000,
+ .pa_end = 0x4900E1ff,
+ .flags = ADDR_TYPE_RT
},
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
- .slaves = omap2430_dss_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
- .masters = omap2430_dss_masters,
- .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
- .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-};
-
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_dss_dispc_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_dispc_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ { }
};
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
- &omap2430_l4_core__dss_dispc,
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_gpio2_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap2430_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &omap2_dispc_hwmod_class,
- .mpu_irqs = omap2_dispc_irqs,
- .main_clk = "dss1_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
- },
+/* l4_wkup -> gpio3 */
+static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
+ {
+ .pa_start = 0x49010000,
+ .pa_end = 0x490101ff,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap2430_dss_dispc_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
- .flags = HWMOD_NO_IDLEST,
- .dev_attr = &omap2_3_dss_dispc_dev_attr
+ { }
};
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_dss_rfbi_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_rfbi_addrs,
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_gpio3_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio3_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
- &omap2430_l4_core__dss_rfbi,
-};
-
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
- { .role = "ick", .clk = "dss_ick" },
-};
-
-static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap2_rfbi_hwmod_class,
- .main_clk = "dss1_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
- .module_offs = CORE_MOD,
- },
+/* l4_wkup -> gpio4 */
+static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
+ {
+ .pa_start = 0x49012000,
+ .pa_end = 0x490121ff,
+ .flags = ADDR_TYPE_RT
},
- .opt_clks = dss_rfbi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
- .slaves = omap2430_dss_rfbi_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
- .flags = HWMOD_NO_IDLEST,
+ { }
};
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_dss_venc_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_venc_addrs,
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_gpio4_hwmod,
+ .clk = "gpios_ick",
+ .addr = omap2430_gpio4_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
- &omap2430_l4_core__dss_venc,
-};
-
-static struct omap_hwmod omap2430_dss_venc_hwmod = {
- .name = "dss_venc",
- .class = &omap2_venc_hwmod_class,
- .main_clk = "dss_54m_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
- .module_offs = CORE_MOD,
- },
+/* l4_core -> gpio5 */
+static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
+ {
+ .pa_start = 0x480B6000,
+ .pa_end = 0x480B61ff,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap2430_dss_venc_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves),
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* I2C common */
-static struct omap_hwmod_class_sysconfig i2c_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x20,
- .syss_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
+ { }
};
-static struct omap_hwmod_class i2c_class = {
- .name = "i2c",
- .sysc = &i2c_sysc,
- .rev = OMAP_I2C_IP_VERSION_1,
- .reset = &omap_i2c_reset,
+static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_gpio5_hwmod,
+ .clk = "gpio5_ick",
+ .addr = omap2430_gpio5_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_i2c_dev_attr i2c_dev_attr = {
- .fifo_depth = 8, /* bytes */
- .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
- OMAP_I2C_FLAG_BUS_SHIFT_2 |
- OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
+ .master = &omap2430_dma_system_hwmod,
+ .slave = &omap2xxx_l3_main_hwmod,
+ .clk = "core_l3_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* I2C1 */
-
-static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
- &omap2430_l4_core__i2c1,
-};
-
-static struct omap_hwmod omap2430_i2c1_hwmod = {
- .name = "i2c1",
- .flags = HWMOD_16BIT_REG,
- .mpu_irqs = omap2_i2c1_mpu_irqs,
- .sdma_reqs = omap2_i2c1_sdma_reqs,
- .main_clk = "i2chs1_fck",
- .prcm = {
- .omap2 = {
- /*
- * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
- * I2CHS IP's do not follow the usual pattern.
- * prcm_reg_id alone cannot be used to program
- * the iclk and fclk. Needs to be handled using
- * additional flags when clk handling is moved
- * to hwmod framework.
- */
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
- },
- },
- .slaves = omap2430_i2c1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
- .class = &i2c_class,
- .dev_attr = &i2c_dev_attr,
-};
-
-/* I2C2 */
-
-static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
- &omap2430_l4_core__i2c2,
-};
-
-static struct omap_hwmod omap2430_i2c2_hwmod = {
- .name = "i2c2",
- .flags = HWMOD_16BIT_REG,
- .mpu_irqs = omap2_i2c2_mpu_irqs,
- .sdma_reqs = omap2_i2c2_sdma_reqs,
- .main_clk = "i2chs2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
- },
- },
- .slaves = omap2430_i2c2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
- .class = &i2c_class,
- .dev_attr = &i2c_dev_attr,
-};
-
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
- {
- .pa_start = 0x4900C000,
- .pa_end = 0x4900C1ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
- .master = &omap2430_l4_wkup_hwmod,
- .slave = &omap2430_gpio1_hwmod,
- .clk = "gpios_ick",
- .addr = omap2430_gpio1_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio2 */
-static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
- {
- .pa_start = 0x4900E000,
- .pa_end = 0x4900E1ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
- .master = &omap2430_l4_wkup_hwmod,
- .slave = &omap2430_gpio2_hwmod,
- .clk = "gpios_ick",
- .addr = omap2430_gpio2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio3 */
-static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
- {
- .pa_start = 0x49010000,
- .pa_end = 0x490101ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
- .master = &omap2430_l4_wkup_hwmod,
- .slave = &omap2430_gpio3_hwmod,
- .clk = "gpios_ick",
- .addr = omap2430_gpio3_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio4 */
-static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
- {
- .pa_start = 0x49012000,
- .pa_end = 0x490121ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
- .master = &omap2430_l4_wkup_hwmod,
- .slave = &omap2430_gpio4_hwmod,
- .clk = "gpios_ick",
- .addr = omap2430_gpio4_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> gpio5 */
-static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
- {
- .pa_start = 0x480B6000,
- .pa_end = 0x480B61ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_gpio5_hwmod,
- .clk = "gpio5_ick",
- .addr = omap2430_gpio5_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
- .bank_width = 32,
- .dbck_flag = false,
-};
-
-/* gpio1 */
-static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
- &omap2430_l4_wkup__gpio1,
-};
-
-static struct omap_hwmod omap2430_gpio1_hwmod = {
- .name = "gpio1",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio1_irqs,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
- },
- },
- .slaves = omap2430_gpio1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
- .class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
-
-/* gpio2 */
-static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
- &omap2430_l4_wkup__gpio2,
-};
-
-static struct omap_hwmod omap2430_gpio2_hwmod = {
- .name = "gpio2",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio2_irqs,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .slaves = omap2430_gpio2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
- .class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
-
-/* gpio3 */
-static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
- &omap2430_l4_wkup__gpio3,
-};
-
-static struct omap_hwmod omap2430_gpio3_hwmod = {
- .name = "gpio3",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio3_irqs,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .slaves = omap2430_gpio3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
- .class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
-
-/* gpio4 */
-static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
- &omap2430_l4_wkup__gpio4,
-};
-
-static struct omap_hwmod omap2430_gpio4_hwmod = {
- .name = "gpio4",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio4_irqs,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .slaves = omap2430_gpio4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
- .class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
-
-/* gpio5 */
-static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
- { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
- { .irq = -1 }
-};
-
-static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
- &omap2430_l4_core__gpio5,
-};
-
-static struct omap_hwmod omap2430_gpio5_hwmod = {
- .name = "gpio5",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap243x_gpio5_irqs,
- .main_clk = "gpio5_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 2,
- .module_bit = OMAP2430_EN_GPIO5_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
- },
- },
- .slaves = omap2430_gpio5_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
- .class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
-
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
- .master = &omap2430_dma_system_hwmod,
- .slave = &omap2430_l3_main_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
- &omap2430_dma_system__l3,
-};
-
-/* l4_core -> dma_system */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_dma_system_hwmod,
- .clk = "sdma_ick",
- .addr = omap2_dma_system_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
- &omap2430_l4_core__dma_system,
-};
-
-static struct omap_hwmod omap2430_dma_system_hwmod = {
- .name = "dma",
- .class = &omap2xxx_dma_hwmod_class,
- .mpu_irqs = omap2_dma_system_irqs,
- .main_clk = "core_l3_ck",
- .slaves = omap2430_dma_system_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
- .masters = omap2430_dma_system_masters,
- .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
- .dev_attr = &dma_dev_attr,
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* mailbox */
-static struct omap_hwmod omap2430_mailbox_hwmod;
-static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
- { .irq = 26 },
- { .irq = -1 }
+/* l4_core -> dma_system */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_dma_system_hwmod,
+ .clk = "sdma_ick",
+ .addr = omap2_dma_system_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> mailbox */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_mailbox_hwmod,
- .addr = omap2_mailbox_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
- &omap2430_l4_core__mailbox,
-};
-
-static struct omap_hwmod omap2430_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap2xxx_mailbox_hwmod_class,
- .mpu_irqs = omap2430_mailbox_irqs,
- .main_clk = "mailboxes_ick",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
- },
- },
- .slaves = omap2430_mailbox_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
-};
-
-/* mcspi1 */
-static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
- &omap2430_l4_core__mcspi1,
-};
-
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
- .num_chipselect = 4,
-};
-
-static struct omap_hwmod omap2430_mcspi1_hwmod = {
- .name = "mcspi1_hwmod",
- .mpu_irqs = omap2_mcspi1_mpu_irqs,
- .sdma_reqs = omap2_mcspi1_sdma_reqs,
- .main_clk = "mcspi1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
- },
- },
- .slaves = omap2430_mcspi1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
- .class = &omap2xxx_mcspi_class,
- .dev_attr = &omap_mcspi1_dev_attr,
-};
-
-/* mcspi2 */
-static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
- &omap2430_l4_core__mcspi2,
-};
-
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
- .num_chipselect = 2,
-};
-
-static struct omap_hwmod omap2430_mcspi2_hwmod = {
- .name = "mcspi2_hwmod",
- .mpu_irqs = omap2_mcspi2_mpu_irqs,
- .sdma_reqs = omap2_mcspi2_sdma_reqs,
- .main_clk = "mcspi2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
- },
- },
- .slaves = omap2430_mcspi2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
- .class = &omap2xxx_mcspi_class,
- .dev_attr = &omap_mcspi2_dev_attr,
-};
-
-/* mcspi3 */
-static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
- { .irq = 91 },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
- { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
- { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
- { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
- { .dma_req = -1 }
-};
-
-static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
- &omap2430_l4_core__mcspi3,
-};
-
-static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
- .num_chipselect = 2,
-};
-
-static struct omap_hwmod omap2430_mcspi3_hwmod = {
- .name = "mcspi3_hwmod",
- .mpu_irqs = omap2430_mcspi3_mpu_irqs,
- .sdma_reqs = omap2430_mcspi3_sdma_reqs,
- .main_clk = "mcspi3_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 2,
- .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
- },
- },
- .slaves = omap2430_mcspi3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
- .class = &omap2xxx_mcspi_class,
- .dev_attr = &omap_mcspi3_dev_attr,
-};
-
-/*
- * usbhsotg
- */
-static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
- .rev_offs = 0x0400,
- .sysc_offs = 0x0404,
- .syss_offs = 0x0408,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class usbotg_class = {
- .name = "usbotg",
- .sysc = &omap2430_usbhsotg_sysc,
-};
-
-/* usb_otg_hs */
-static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
-
- { .name = "mc", .irq = 92 },
- { .name = "dma", .irq = 93 },
- { .irq = -1 }
-};
-
-static struct omap_hwmod omap2430_usbhsotg_hwmod = {
- .name = "usb_otg_hs",
- .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
- .main_clk = "usbhs_ick",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_USBHS_MASK,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
- },
- },
- .masters = omap2430_usbhsotg_masters,
- .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
- .slaves = omap2430_usbhsotg_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
- .class = &usbotg_class,
- /*
- * Erratum ID: i479 idle_req / idle_ack mechanism potentially
- * broken when autoidle is enabled
- * workaround is to disable the autoidle bit at module level.
- */
- .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
- | HWMOD_SWSUP_MSTANDBY,
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
- .rev_offs = 0x007C,
- .sysc_offs = 0x008C,
- .sysc_flags = (SYSC_HAS_SOFTRESET),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
- .name = "mcbsp",
- .sysc = &omap2430_mcbsp_sysc,
- .rev = MCBSP_CONFIG_TYPE2,
-};
-
-/* mcbsp1 */
-static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
- { .name = "tx", .irq = 59 },
- { .name = "rx", .irq = 60 },
- { .name = "ovr", .irq = 61 },
- { .name = "common", .irq = 64 },
- { .irq = -1 }
-};
-
-/* l4_core -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
- .master = &omap2430_l4_core_hwmod,
- .slave = &omap2430_mcbsp1_hwmod,
- .clk = "mcbsp1_ick",
- .addr = omap2_mcbsp1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
- &omap2430_l4_core__mcbsp1,
-};
-
-static struct omap_hwmod omap2430_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap2430_mcbsp_hwmod_class,
- .mpu_irqs = omap2430_mcbsp1_irqs,
- .sdma_reqs = omap2_mcbsp1_sdma_reqs,
- .main_clk = "mcbsp1_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
- },
- },
- .slaves = omap2430_mcbsp1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
+static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_mailbox_hwmod,
+ .addr = omap2_mailbox_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp2 */
-static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
- { .name = "tx", .irq = 62 },
- { .name = "rx", .irq = 63 },
- { .name = "common", .irq = 16 },
- { .irq = -1 }
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_mcbsp1_hwmod,
+ .clk = "mcbsp1_ick",
+ .addr = omap2_mcbsp1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> mcbsp2 */
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
- .master = &omap2430_l4_core_hwmod,
+ .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2430_mcbsp2_hwmod,
.clk = "mcbsp2_ick",
.addr = omap2xxx_mcbsp2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
- &omap2430_l4_core__mcbsp2,
-};
-
-static struct omap_hwmod omap2430_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap2430_mcbsp_hwmod_class,
- .mpu_irqs = omap2430_mcbsp2_irqs,
- .sdma_reqs = omap2_mcbsp2_sdma_reqs,
- .main_clk = "mcbsp2_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
- },
- },
- .slaves = omap2430_mcbsp2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
-};
-
-/* mcbsp3 */
-static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
- { .name = "tx", .irq = 89 },
- { .name = "rx", .irq = 90 },
- { .name = "common", .irq = 17 },
- { .irq = -1 }
-};
-
static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
{
.name = "mpu",
/* l4_core -> mcbsp3 */
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
- .master = &omap2430_l4_core_hwmod,
+ .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2430_mcbsp3_hwmod,
.clk = "mcbsp3_ick",
.addr = omap2430_mcbsp3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp3 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
- &omap2430_l4_core__mcbsp3,
-};
-
-static struct omap_hwmod omap2430_mcbsp3_hwmod = {
- .name = "mcbsp3",
- .class = &omap2430_mcbsp_hwmod_class,
- .mpu_irqs = omap2430_mcbsp3_irqs,
- .sdma_reqs = omap2_mcbsp3_sdma_reqs,
- .main_clk = "mcbsp3_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
- },
- },
- .slaves = omap2430_mcbsp3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
-};
-
-/* mcbsp4 */
-static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
- { .name = "tx", .irq = 54 },
- { .name = "rx", .irq = 55 },
- { .name = "common", .irq = 18 },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
- { .name = "rx", .dma_req = 20 },
- { .name = "tx", .dma_req = 19 },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
{
.name = "mpu",
/* l4_core -> mcbsp4 */
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
- .master = &omap2430_l4_core_hwmod,
+ .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2430_mcbsp4_hwmod,
.clk = "mcbsp4_ick",
.addr = omap2430_mcbsp4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp4 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
- &omap2430_l4_core__mcbsp4,
-};
-
-static struct omap_hwmod omap2430_mcbsp4_hwmod = {
- .name = "mcbsp4",
- .class = &omap2430_mcbsp_hwmod_class,
- .mpu_irqs = omap2430_mcbsp4_irqs,
- .sdma_reqs = omap2430_mcbsp4_sdma_chs,
- .main_clk = "mcbsp4_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
- },
- },
- .slaves = omap2430_mcbsp4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
-};
-
-/* mcbsp5 */
-static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
- { .name = "tx", .irq = 81 },
- { .name = "rx", .irq = 82 },
- { .name = "common", .irq = 19 },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
- { .name = "rx", .dma_req = 22 },
- { .name = "tx", .dma_req = 21 },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
{
.name = "mpu",
/* l4_core -> mcbsp5 */
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
- .master = &omap2430_l4_core_hwmod,
+ .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2430_mcbsp5_hwmod,
.clk = "mcbsp5_ick",
.addr = omap2430_mcbsp5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp5 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
- &omap2430_l4_core__mcbsp5,
+/* l4_core -> hdq1w */
+static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2430_hdq1w_hwmod,
+ .clk = "hdq_ick",
+ .addr = omap2_hdq1w_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
-static struct omap_hwmod omap2430_mcbsp5_hwmod = {
- .name = "mcbsp5",
- .class = &omap2430_mcbsp_hwmod_class,
- .mpu_irqs = omap2430_mcbsp5_irqs,
- .sdma_reqs = omap2430_mcbsp5_sdma_chs,
- .main_clk = "mcbsp5_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
- },
+/* l4_wkup -> 32ksync_counter */
+static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
+ {
+ .pa_start = 0x49020000,
+ .pa_end = 0x4902001f,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap2430_mcbsp5_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
-};
-
-/* MMC/SD/SDIO common */
-
-static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
- .rev_offs = 0x1fc,
- .sysc_offs = 0x10,
- .syss_offs = 0x14,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_mmc_class = {
- .name = "mmc",
- .sysc = &omap2430_mmc_sysc,
-};
-
-/* MMC/SD/SDIO1 */
-
-static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
- { .irq = 83 },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
- { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
- { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
- { .dma_req = -1 }
+ { }
};
-static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
- { .role = "dbck", .clk = "mmchsdb1_fck" },
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
+ .master = &omap2xxx_l4_wkup_hwmod,
+ .slave = &omap2xxx_counter_32k_hwmod,
+ .clk = "sync_32k_ick",
+ .addr = omap2430_counter_32k_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
+static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
+ &omap2xxx_l3_main__l4_core,
+ &omap2xxx_mpu__l3_main,
+ &omap2xxx_dss__l3,
+ &omap2430_usbhsotg__l3,
+ &omap2430_l4_core__i2c1,
+ &omap2430_l4_core__i2c2,
+ &omap2xxx_l4_core__l4_wkup,
+ &omap2_l4_core__uart1,
+ &omap2_l4_core__uart2,
+ &omap2_l4_core__uart3,
+ &omap2430_l4_core__usbhsotg,
&omap2430_l4_core__mmc1,
-};
-
-static struct omap_mmc_dev_attr mmc1_dev_attr = {
- .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-
-static struct omap_hwmod omap2430_mmc1_hwmod = {
- .name = "mmc1",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2430_mmc1_mpu_irqs,
- .sdma_reqs = omap2430_mmc1_sdma_reqs,
- .opt_clks = omap2430_mmc1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
- .main_clk = "mmchs1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 2,
- .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
- },
- },
- .dev_attr = &mmc1_dev_attr,
- .slaves = omap2430_mmc1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
- .class = &omap2430_mmc_class,
-};
-
-/* MMC/SD/SDIO2 */
-
-static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
- { .irq = 86 },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
- { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
- { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
- { .dma_req = -1 }
-};
-
-static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
- { .role = "dbck", .clk = "mmchsdb2_fck" },
-};
-
-static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
&omap2430_l4_core__mmc2,
-};
-
-static struct omap_hwmod omap2430_mmc2_hwmod = {
- .name = "mmc2",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2430_mmc2_mpu_irqs,
- .sdma_reqs = omap2430_mmc2_sdma_reqs,
- .opt_clks = omap2430_mmc2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
- .main_clk = "mmchs2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 2,
- .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
- },
- },
- .slaves = omap2430_mmc2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
- .class = &omap2430_mmc_class,
-};
-
-static __initdata struct omap_hwmod *omap2430_hwmods[] = {
- &omap2430_l3_main_hwmod,
- &omap2430_l4_core_hwmod,
- &omap2430_l4_wkup_hwmod,
- &omap2430_mpu_hwmod,
- &omap2430_iva_hwmod,
-
- &omap2430_timer1_hwmod,
- &omap2430_timer2_hwmod,
- &omap2430_timer3_hwmod,
- &omap2430_timer4_hwmod,
- &omap2430_timer5_hwmod,
- &omap2430_timer6_hwmod,
- &omap2430_timer7_hwmod,
- &omap2430_timer8_hwmod,
- &omap2430_timer9_hwmod,
- &omap2430_timer10_hwmod,
- &omap2430_timer11_hwmod,
- &omap2430_timer12_hwmod,
-
- &omap2430_wd_timer2_hwmod,
- &omap2430_uart1_hwmod,
- &omap2430_uart2_hwmod,
- &omap2430_uart3_hwmod,
- /* dss class */
- &omap2430_dss_core_hwmod,
- &omap2430_dss_dispc_hwmod,
- &omap2430_dss_rfbi_hwmod,
- &omap2430_dss_venc_hwmod,
- /* i2c class */
- &omap2430_i2c1_hwmod,
- &omap2430_i2c2_hwmod,
- &omap2430_mmc1_hwmod,
- &omap2430_mmc2_hwmod,
-
- /* gpio class */
- &omap2430_gpio1_hwmod,
- &omap2430_gpio2_hwmod,
- &omap2430_gpio3_hwmod,
- &omap2430_gpio4_hwmod,
- &omap2430_gpio5_hwmod,
-
- /* dma_system class*/
- &omap2430_dma_system_hwmod,
-
- /* mcbsp class */
- &omap2430_mcbsp1_hwmod,
- &omap2430_mcbsp2_hwmod,
- &omap2430_mcbsp3_hwmod,
- &omap2430_mcbsp4_hwmod,
- &omap2430_mcbsp5_hwmod,
-
- /* mailbox class */
- &omap2430_mailbox_hwmod,
-
- /* mcspi class */
- &omap2430_mcspi1_hwmod,
- &omap2430_mcspi2_hwmod,
- &omap2430_mcspi3_hwmod,
-
- /* usbotg class*/
- &omap2430_usbhsotg_hwmod,
-
+ &omap2xxx_l4_core__mcspi1,
+ &omap2xxx_l4_core__mcspi2,
+ &omap2430_l4_core__mcspi3,
+ &omap2430_l3__iva,
+ &omap2430_l4_wkup__timer1,
+ &omap2xxx_l4_core__timer2,
+ &omap2xxx_l4_core__timer3,
+ &omap2xxx_l4_core__timer4,
+ &omap2xxx_l4_core__timer5,
+ &omap2xxx_l4_core__timer6,
+ &omap2xxx_l4_core__timer7,
+ &omap2xxx_l4_core__timer8,
+ &omap2xxx_l4_core__timer9,
+ &omap2xxx_l4_core__timer10,
+ &omap2xxx_l4_core__timer11,
+ &omap2xxx_l4_core__timer12,
+ &omap2430_l4_wkup__wd_timer2,
+ &omap2xxx_l4_core__dss,
+ &omap2xxx_l4_core__dss_dispc,
+ &omap2xxx_l4_core__dss_rfbi,
+ &omap2xxx_l4_core__dss_venc,
+ &omap2430_l4_wkup__gpio1,
+ &omap2430_l4_wkup__gpio2,
+ &omap2430_l4_wkup__gpio3,
+ &omap2430_l4_wkup__gpio4,
+ &omap2430_l4_core__gpio5,
+ &omap2430_dma_system__l3,
+ &omap2430_l4_core__dma_system,
+ &omap2430_l4_core__mailbox,
+ &omap2430_l4_core__mcbsp1,
+ &omap2430_l4_core__mcbsp2,
+ &omap2430_l4_core__mcbsp3,
+ &omap2430_l4_core__mcbsp4,
+ &omap2430_l4_core__mcbsp5,
+ &omap2430_l4_core__hdq1w,
+ &omap2430_l4_wkup__counter_32k,
NULL,
};
int __init omap2430_hwmod_init(void)
{
- return omap_hwmod_register(omap2430_hwmods);
+ return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
}
},
{ }
};
+
+struct omap_hwmod_addr_space omap2_hdq1w_addr_space[] = {
+ {
+ .pa_start = 0x480b2000,
+ .pa_end = 0x480b2fff,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
* omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
*
* Copyright (C) 2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
#include <plat/serial.h>
#include <plat/dma.h>
#include <plat/common.h>
+#include <plat/hdq1w.h>
#include <mach/irqs.h>
{ .irq = -1 }
};
+struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x14,
+ .syss_offs = 0x18,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_hdq1w_class = {
+ .name = "hdq1w",
+ .sysc = &omap2_hdq1w_sysc,
+ .reset = &omap_hdq1w_reset,
+};
+
+struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
+ { .irq = 58, },
+ { .irq = -1 }
+};
+
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
+#include <plat/l3_2xxx.h>
+#include <plat/l4_2xxx.h>
#include "omap_hwmod_common_data.h"
-struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
{
.pa_start = OMAP2_UART1_BASE,
.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
{ }
};
-struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
{
.pa_start = OMAP2_UART2_BASE,
.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
{ }
};
-struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
{
.pa_start = OMAP2_UART3_BASE,
.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
{ }
};
-struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
{
.pa_start = 0x4802a000,
.pa_end = 0x4802a000 + SZ_1K - 1,
{ }
};
-struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
{
.pa_start = 0x48078000,
.pa_end = 0x48078000 + SZ_1K - 1,
{ }
};
-struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
{
.pa_start = 0x4807a000,
.pa_end = 0x4807a000 + SZ_1K - 1,
{ }
};
-struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
{
.pa_start = 0x4807c000,
.pa_end = 0x4807c000 + SZ_1K - 1,
{ }
};
-struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
{
.pa_start = 0x4807e000,
.pa_end = 0x4807e000 + SZ_1K - 1,
{ }
};
-struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
{
.pa_start = 0x48080000,
.pa_end = 0x48080000 + SZ_1K - 1,
{ }
};
-struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
{
.pa_start = 0x48082000,
.pa_end = 0x48082000 + SZ_1K - 1,
{ }
};
-struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
{
.pa_start = 0x48084000,
.pa_end = 0x48084000 + SZ_1K - 1,
{ }
};
+/*
+ * Common interconnect data
+ */
+
+/* L3 -> L4_CORE interface */
+struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
+ .master = &omap2xxx_l3_main_hwmod,
+ .slave = &omap2xxx_l4_core_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* MPU -> L3 interface */
+struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
+ .master = &omap2xxx_mpu_hwmod,
+ .slave = &omap2xxx_l3_main_hwmod,
+ .user = OCP_USER_MPU,
+};
+
+/* DSS -> l3 */
+struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
+ .master = &omap2xxx_dss_core_hwmod,
+ .slave = &omap2xxx_l3_main_hwmod,
+ .fw = {
+ .omap2 = {
+ .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
+ .flags = OMAP_FIREWALL_L3,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4_CORE -> L4_WKUP interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_l4_wkup_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART1 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_uart1_hwmod,
+ .clk = "uart1_ick",
+ .addr = omap2xxx_uart1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_uart2_hwmod,
+ .clk = "uart2_ick",
+ .addr = omap2xxx_uart2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_uart3_hwmod,
+ .clk = "uart3_ick",
+ .addr = omap2xxx_uart3_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi1 interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_mcspi1_hwmod,
+ .clk = "mcspi1_ick",
+ .addr = omap2_mcspi1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi2 interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_mcspi2_hwmod,
+ .clk = "mcspi2_ick",
+ .addr = omap2_mcspi2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer2 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer2_hwmod,
+ .clk = "gpt2_ick",
+ .addr = omap2xxx_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer3 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer3_hwmod,
+ .clk = "gpt3_ick",
+ .addr = omap2xxx_timer3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer4 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer4_hwmod,
+ .clk = "gpt4_ick",
+ .addr = omap2xxx_timer4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer5 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer5_hwmod,
+ .clk = "gpt5_ick",
+ .addr = omap2xxx_timer5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer6 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer6_hwmod,
+ .clk = "gpt6_ick",
+ .addr = omap2xxx_timer6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer7 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer7_hwmod,
+ .clk = "gpt7_ick",
+ .addr = omap2xxx_timer7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer8 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer8_hwmod,
+ .clk = "gpt8_ick",
+ .addr = omap2xxx_timer8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer9 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer9_hwmod,
+ .clk = "gpt9_ick",
+ .addr = omap2xxx_timer9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer10 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer10_hwmod,
+ .clk = "gpt10_ick",
+ .addr = omap2_timer10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer11 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer11_hwmod,
+ .clk = "gpt11_ick",
+ .addr = omap2_timer11_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer12 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_timer12_hwmod,
+ .clk = "gpt12_ick",
+ .addr = omap2xxx_timer12_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_dss_core_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2_dss_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_dispc */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_dss_dispc_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2_dss_dispc_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_rfbi */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_dss_rfbi_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2_dss_rfbi_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_venc */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_dss_venc_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2_dss_venc_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
*/
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
+#include <plat/gpio.h>
#include <plat/dma.h>
#include <plat/dmtimer.h>
#include <plat/mcspi.h>
#include <mach/irqs.h>
#include "omap_hwmod_common_data.h"
+#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
#include "wd_timer.h"
struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap2xxx_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable
+ .pre_shutdown = &omap2_wd_timer_disable,
+ .reset = &omap2_wd_timer_reset,
};
/*
.sysc = &omap2xxx_mcspi_sysc,
.rev = OMAP2_MCSPI_REV,
};
+
+/*
+ * IP blocks
+ */
+
+/* L3 */
+struct omap_hwmod omap2xxx_l3_main_hwmod = {
+ .name = "l3_main",
+ .class = &l3_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
+};
+
+/* L4 CORE */
+struct omap_hwmod omap2xxx_l4_core_hwmod = {
+ .name = "l4_core",
+ .class = &l4_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
+};
+
+/* L4 WKUP */
+struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &l4_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
+};
+
+/* MPU */
+struct omap_hwmod omap2xxx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &mpu_hwmod_class,
+ .main_clk = "mpu_ck",
+};
+
+/* IVA2 */
+struct omap_hwmod omap2xxx_iva_hwmod = {
+ .name = "iva",
+ .class = &iva_hwmod_class,
+};
+
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+ .timer_capability = OMAP_TIMER_ALWON,
+};
+
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+ .timer_capability = OMAP_TIMER_HAS_PWM,
+};
+
+/* timer1 */
+
+struct omap_hwmod omap2xxx_timer1_hwmod = {
+ .name = "timer1",
+ .mpu_irqs = omap2_timer1_mpu_irqs,
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer2 */
+
+struct omap_hwmod omap2xxx_timer2_hwmod = {
+ .name = "timer2",
+ .mpu_irqs = omap2_timer2_mpu_irqs,
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer3 */
+
+struct omap_hwmod omap2xxx_timer3_hwmod = {
+ .name = "timer3",
+ .mpu_irqs = omap2_timer3_mpu_irqs,
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer4 */
+
+struct omap_hwmod omap2xxx_timer4_hwmod = {
+ .name = "timer4",
+ .mpu_irqs = omap2_timer4_mpu_irqs,
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer5 */
+
+struct omap_hwmod omap2xxx_timer5_hwmod = {
+ .name = "timer5",
+ .mpu_irqs = omap2_timer5_mpu_irqs,
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer6 */
+
+struct omap_hwmod omap2xxx_timer6_hwmod = {
+ .name = "timer6",
+ .mpu_irqs = omap2_timer6_mpu_irqs,
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer7 */
+
+struct omap_hwmod omap2xxx_timer7_hwmod = {
+ .name = "timer7",
+ .mpu_irqs = omap2_timer7_mpu_irqs,
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer8 */
+
+struct omap_hwmod omap2xxx_timer8_hwmod = {
+ .name = "timer8",
+ .mpu_irqs = omap2_timer8_mpu_irqs,
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer9 */
+
+struct omap_hwmod omap2xxx_timer9_hwmod = {
+ .name = "timer9",
+ .mpu_irqs = omap2_timer9_mpu_irqs,
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+ },
+ },
+ .dev_attr = &capability_pwm_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer10 */
+
+struct omap_hwmod omap2xxx_timer10_hwmod = {
+ .name = "timer10",
+ .mpu_irqs = omap2_timer10_mpu_irqs,
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+ },
+ },
+ .dev_attr = &capability_pwm_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer11 */
+
+struct omap_hwmod omap2xxx_timer11_hwmod = {
+ .name = "timer11",
+ .mpu_irqs = omap2_timer11_mpu_irqs,
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+ },
+ },
+ .dev_attr = &capability_pwm_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer12 */
+
+struct omap_hwmod omap2xxx_timer12_hwmod = {
+ .name = "timer12",
+ .mpu_irqs = omap2xxx_timer12_mpu_irqs,
+ .main_clk = "gpt12_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
+ },
+ },
+ .dev_attr = &capability_pwm_dev_attr,
+ .class = &omap2xxx_timer_hwmod_class,
+};
+
+/* wd_timer2 */
+struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
+ .name = "wd_timer2",
+ .class = &omap2xxx_wd_timer_hwmod_class,
+ .main_clk = "mpu_wdt_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
+ },
+ },
+};
+
+/* UART1 */
+
+struct omap_hwmod omap2xxx_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = omap2_uart1_sdma_reqs,
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_UART1_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+ },
+ },
+ .class = &omap2_uart_class,
+};
+
+/* UART2 */
+
+struct omap_hwmod omap2xxx_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = omap2_uart2_sdma_reqs,
+ .main_clk = "uart2_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_UART2_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+ },
+ },
+ .class = &omap2_uart_class,
+};
+
+/* UART3 */
+
+struct omap_hwmod omap2xxx_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = omap2_uart3_sdma_reqs,
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 2,
+ .module_bit = OMAP24XX_EN_UART3_SHIFT,
+ .idlest_reg_id = 2,
+ .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+ },
+ },
+ .class = &omap2_uart_class,
+};
+
+/* dss */
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+ /*
+ * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+ * driver does not use these clocks.
+ */
+ { .role = "tv_clk", .clk = "dss_54m_fck" },
+ { .role = "sys_clk", .clk = "dss2_fck" },
+};
+
+struct omap_hwmod omap2xxx_dss_core_hwmod = {
+ .name = "dss_core",
+ .class = &omap2_dss_hwmod_class,
+ .main_clk = "dss1_fck", /* instead of dss_fck */
+ .sdma_reqs = omap2xxx_dss_sdma_chs,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+ },
+ },
+ .opt_clks = dss_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+ .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+};
+
+struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap2_dispc_hwmod_class,
+ .mpu_irqs = omap2_dispc_irqs,
+ .main_clk = "dss1_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+ },
+ },
+ .flags = HWMOD_NO_IDLEST,
+ .dev_attr = &omap2_3_dss_dispc_dev_attr
+};
+
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+ { .role = "ick", .clk = "dss_ick" },
+};
+
+struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
+ .name = "dss_rfbi",
+ .class = &omap2_rfbi_hwmod_class,
+ .main_clk = "dss1_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+ .module_offs = CORE_MOD,
+ },
+ },
+ .opt_clks = dss_rfbi_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
+ .flags = HWMOD_NO_IDLEST,
+};
+
+struct omap_hwmod omap2xxx_dss_venc_hwmod = {
+ .name = "dss_venc",
+ .class = &omap2_venc_hwmod_class,
+ .main_clk = "dss_54m_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+ .module_offs = CORE_MOD,
+ },
+ },
+ .flags = HWMOD_NO_IDLEST,
+};
+
+/* gpio dev_attr */
+struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = false,
+};
+
+/* gpio1 */
+struct omap_hwmod omap2xxx_gpio1_hwmod = {
+ .name = "gpio1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2_gpio1_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &omap2xxx_gpio_dev_attr,
+};
+
+/* gpio2 */
+struct omap_hwmod omap2xxx_gpio2_hwmod = {
+ .name = "gpio2",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2_gpio2_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &omap2xxx_gpio_dev_attr,
+};
+
+/* gpio3 */
+struct omap_hwmod omap2xxx_gpio3_hwmod = {
+ .name = "gpio3",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2_gpio3_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &omap2xxx_gpio_dev_attr,
+};
+
+/* gpio4 */
+struct omap_hwmod omap2xxx_gpio4_hwmod = {
+ .name = "gpio4",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2_gpio4_irqs,
+ .main_clk = "gpios_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+ },
+ },
+ .class = &omap2xxx_gpio_hwmod_class,
+ .dev_attr = &omap2xxx_gpio_dev_attr,
+};
+
+/* mcspi1 */
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+ .num_chipselect = 4,
+};
+
+struct omap_hwmod omap2xxx_mcspi1_hwmod = {
+ .name = "mcspi1",
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap2_mcspi1_sdma_reqs,
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
+ },
+ },
+ .class = &omap2xxx_mcspi_class,
+ .dev_attr = &omap_mcspi1_dev_attr,
+};
+
+/* mcspi2 */
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+ .num_chipselect = 2,
+};
+
+struct omap_hwmod omap2xxx_mcspi2_hwmod = {
+ .name = "mcspi2",
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap2_mcspi2_sdma_reqs,
+ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
+ },
+ },
+ .class = &omap2xxx_mcspi_class,
+ .dev_attr = &omap_mcspi2_dev_attr,
+};
+
+
+static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
+ .name = "counter",
+};
+
+struct omap_hwmod omap2xxx_counter_32k_hwmod = {
+ .name = "counter_32k",
+ .main_clk = "func_32k_ck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = WKUP_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
+ },
+ },
+ .class = &omap2xxx_counter_hwmod_class,
+};
* omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
*
* Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
/*
* OMAP3xxx hardware module integration data
*
- * ALl of the data in this section should be autogeneratable from the
+ * All of the data in this section should be autogeneratable from the
* TI hardware database or other technical documentation. Data that
* is driver-specific or driver-kernel integration-specific belongs
* elsewhere.
*/
-static struct omap_hwmod omap3xxx_mpu_hwmod;
-static struct omap_hwmod omap3xxx_iva_hwmod;
-static struct omap_hwmod omap3xxx_l3_main_hwmod;
-static struct omap_hwmod omap3xxx_l4_core_hwmod;
-static struct omap_hwmod omap3xxx_l4_per_hwmod;
-static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
-static struct omap_hwmod omap3430es1_dss_core_hwmod;
-static struct omap_hwmod omap3xxx_dss_core_hwmod;
-static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
-static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
-static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
-static struct omap_hwmod omap3xxx_dss_venc_hwmod;
-static struct omap_hwmod omap3xxx_i2c1_hwmod;
-static struct omap_hwmod omap3xxx_i2c2_hwmod;
-static struct omap_hwmod omap3xxx_i2c3_hwmod;
-static struct omap_hwmod omap3xxx_gpio1_hwmod;
-static struct omap_hwmod omap3xxx_gpio2_hwmod;
-static struct omap_hwmod omap3xxx_gpio3_hwmod;
-static struct omap_hwmod omap3xxx_gpio4_hwmod;
-static struct omap_hwmod omap3xxx_gpio5_hwmod;
-static struct omap_hwmod omap3xxx_gpio6_hwmod;
-static struct omap_hwmod omap34xx_sr1_hwmod;
-static struct omap_hwmod omap34xx_sr2_hwmod;
-static struct omap_hwmod omap34xx_mcspi1;
-static struct omap_hwmod omap34xx_mcspi2;
-static struct omap_hwmod omap34xx_mcspi3;
-static struct omap_hwmod omap34xx_mcspi4;
-static struct omap_hwmod omap3xxx_mmc1_hwmod;
-static struct omap_hwmod omap3xxx_mmc2_hwmod;
-static struct omap_hwmod omap3xxx_mmc3_hwmod;
-static struct omap_hwmod am35xx_usbhsotg_hwmod;
-
-static struct omap_hwmod omap3xxx_dma_system_hwmod;
-
-static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
-static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
-static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
-
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
- .master = &omap3xxx_l3_main_hwmod,
- .slave = &omap3xxx_l4_core_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L3 -> L4_PER interface */
-static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
- .master = &omap3xxx_l3_main_hwmod,
- .slave = &omap3xxx_l4_per_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
+/*
+ * IP blocks
+ */
-/* L3 taret configuration and error log registers */
+/* L3 */
static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
{ .irq = INT_34XX_L3_DBG_IRQ },
{ .irq = INT_34XX_L3_APP_IRQ },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
- {
- .pa_start = 0x68000000,
- .pa_end = 0x6800ffff,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
- .master = &omap3xxx_mpu_hwmod,
- .slave = &omap3xxx_l3_main_hwmod,
- .addr = omap3xxx_l3_main_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
- &omap3xxx_mpu__l3_main,
-};
-
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
- .master = &omap3xxx_dss_core_hwmod,
- .slave = &omap3xxx_l3_main_hwmod,
- .fw = {
- .omap2 = {
- .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
- .flags = OMAP_FIREWALL_L3,
- }
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
- &omap3xxx_l3_main__l4_core,
- &omap3xxx_l3_main__l4_per,
-};
-
-/* L3 */
static struct omap_hwmod omap3xxx_l3_main_hwmod = {
.name = "l3_main",
.class = &l3_hwmod_class,
.mpu_irqs = omap3xxx_l3_main_irqs,
- .masters = omap3xxx_l3_main_masters,
- .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
- .slaves = omap3xxx_l3_main_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
.flags = HWMOD_NO_IDLEST,
};
-static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
-static struct omap_hwmod omap3xxx_uart1_hwmod;
-static struct omap_hwmod omap3xxx_uart2_hwmod;
-static struct omap_hwmod omap3xxx_uart3_hwmod;
-static struct omap_hwmod omap3xxx_uart4_hwmod;
-static struct omap_hwmod am35xx_uart4_hwmod;
-static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
-
-/* l3_core -> usbhsotg interface */
-static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
- .master = &omap3xxx_usbhsotg_hwmod,
- .slave = &omap3xxx_l3_main_hwmod,
- .clk = "core_l3_ick",
- .user = OCP_USER_MPU,
+/* L4 CORE */
+static struct omap_hwmod omap3xxx_l4_core_hwmod = {
+ .name = "l4_core",
+ .class = &l4_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
};
-/* l3_core -> am35xx_usbhsotg interface */
-static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
- .master = &am35xx_usbhsotg_hwmod,
- .slave = &omap3xxx_l3_main_hwmod,
- .clk = "core_l3_ick",
- .user = OCP_USER_MPU,
-};
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_l4_wkup_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* L4 PER */
+static struct omap_hwmod omap3xxx_l4_per_hwmod = {
+ .name = "l4_per",
+ .class = &l4_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
};
-/* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_mmc1_hwmod,
- .clk = "mmchs1_ick",
- .addr = omap2430_mmc1_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
- .flags = OMAP_FIREWALL_L4
+/* L4 WKUP */
+static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &l4_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
};
-/* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_mmc2_hwmod,
- .clk = "mmchs2_ick",
- .addr = omap2430_mmc2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
- .flags = OMAP_FIREWALL_L4
+/* L4 SEC */
+static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
+ .name = "l4_sec",
+ .class = &l4_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
};
-/* L4 CORE -> MMC3 interface */
-static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
- {
- .pa_start = 0x480ad000,
- .pa_end = 0x480ad1ff,
- .flags = ADDR_TYPE_RT,
- },
- { }
+/* MPU */
+static struct omap_hwmod omap3xxx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &mpu_hwmod_class,
+ .main_clk = "arm_fck",
};
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_mmc3_hwmod,
- .clk = "mmchs3_ick",
- .addr = omap3xxx_mmc3_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
- .flags = OMAP_FIREWALL_L4
+/* IVA2 (IVA2) */
+static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
+ { .name = "logic", .rst_shift = 0 },
+ { .name = "seq0", .rst_shift = 1 },
+ { .name = "seq1", .rst_shift = 2 },
};
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
- {
- .pa_start = OMAP3_UART1_BASE,
- .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- },
- { }
+static struct omap_hwmod omap3xxx_iva_hwmod = {
+ .name = "iva",
+ .class = &iva_hwmod_class,
+ .clkdm_name = "iva2_clkdm",
+ .rst_lines = omap3xxx_iva_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
+ .main_clk = "iva2_ck",
};
-static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_uart1_hwmod,
- .clk = "uart1_ick",
- .addr = omap3xxx_uart1_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* timer class */
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
- {
- .pa_start = OMAP3_UART2_BASE,
- .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- },
- { }
+static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap3xxx_timer_1ms_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
};
-static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_uart2_hwmod,
- .clk = "uart2_ick",
- .addr = omap3xxx_uart2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
- {
- .pa_start = OMAP3_UART3_BASE,
- .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- },
- { }
+static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap3xxx_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
};
-static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_uart3_hwmod,
- .clk = "uart3_ick",
- .addr = omap3xxx_uart3_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* secure timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
+ .timer_capability = OMAP_TIMER_SECURE,
};
-/* L4 PER -> UART4 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
- {
- .pa_start = OMAP3_UART4_BASE,
- .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- },
- { }
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+ .timer_capability = OMAP_TIMER_ALWON,
};
-static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_uart4_hwmod,
- .clk = "uart4_ick",
- .addr = omap3xxx_uart4_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+ .timer_capability = OMAP_TIMER_HAS_PWM,
};
-/* AM35xx: L4 CORE -> UART4 interface */
-static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
- {
- .pa_start = OMAP3_UART4_AM35XX_BASE,
- .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+/* timer1 */
+static struct omap_hwmod omap3xxx_timer1_hwmod = {
+ .name = "timer1",
+ .mpu_irqs = omap2_timer1_mpu_irqs,
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
+ },
},
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap3xxx_timer_1ms_hwmod_class,
};
-static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &am35xx_uart4_hwmod,
- .clk = "uart4_ick",
- .addr = am35xx_uart4_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_i2c1_hwmod,
- .clk = "i2c1_ick",
- .addr = omap2_i2c1_addr_space,
- .fw = {
+/* timer2 */
+static struct omap_hwmod omap3xxx_timer2_hwmod = {
+ .name = "timer2",
+ .mpu_irqs = omap2_timer2_mpu_irqs,
+ .main_clk = "gpt2_fck",
+ .prcm = {
.omap2 = {
- .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
- .l4_prot_group = 7,
- .flags = OMAP_FIREWALL_L4,
- }
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT2_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
+ },
},
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap3xxx_timer_1ms_hwmod_class,
};
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_i2c2_hwmod,
- .clk = "i2c2_ick",
- .addr = omap2_i2c2_addr_space,
- .fw = {
+/* timer3 */
+static struct omap_hwmod omap3xxx_timer3_hwmod = {
+ .name = "timer3",
+ .mpu_irqs = omap2_timer3_mpu_irqs,
+ .main_clk = "gpt3_fck",
+ .prcm = {
.omap2 = {
- .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
- .l4_prot_group = 7,
- .flags = OMAP_FIREWALL_L4,
- }
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C3 interface */
-static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
- {
- .pa_start = 0x48060000,
- .pa_end = 0x48060000 + SZ_128 - 1,
- .flags = ADDR_TYPE_RT,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT3_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
+ },
},
- { }
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap3xxx_timer_hwmod_class,
};
-static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_i2c3_hwmod,
- .clk = "i2c3_ick",
- .addr = omap3xxx_i2c3_addr_space,
- .fw = {
+/* timer4 */
+static struct omap_hwmod omap3xxx_timer4_hwmod = {
+ .name = "timer4",
+ .mpu_irqs = omap2_timer4_mpu_irqs,
+ .main_clk = "gpt4_fck",
+ .prcm = {
.omap2 = {
- .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
- .l4_prot_group = 7,
- .flags = OMAP_FIREWALL_L4,
- }
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
- { .irq = 18},
- { .irq = -1 }
-};
-
-static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
- { .irq = 19},
- { .irq = -1 }
-};
-
-/* L4 CORE -> SR1 interface */
-static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
- {
- .pa_start = OMAP34XX_SR1_BASE,
- .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
- .flags = ADDR_TYPE_RT,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT4_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
+ },
},
- { }
-};
-
-static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap34xx_sr1_hwmod,
- .clk = "sr_l4_ick",
- .addr = omap3_sr1_addr_space,
- .user = OCP_USER_MPU,
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap3xxx_timer_hwmod_class,
};
-/* L4 CORE -> SR1 interface */
-static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
- {
- .pa_start = OMAP34XX_SR2_BASE,
- .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
- .flags = ADDR_TYPE_RT,
+/* timer5 */
+static struct omap_hwmod omap3xxx_timer5_hwmod = {
+ .name = "timer5",
+ .mpu_irqs = omap2_timer5_mpu_irqs,
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT5_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
+ },
},
- { }
-};
-
-static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap34xx_sr2_hwmod,
- .clk = "sr_l4_ick",
- .addr = omap3_sr2_addr_space,
- .user = OCP_USER_MPU,
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap3xxx_timer_hwmod_class,
};
-/*
-* usbhsotg interface data
-*/
-
-static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
- {
- .pa_start = OMAP34XX_HSUSB_OTG_BASE,
- .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
+/* timer6 */
+static struct omap_hwmod omap3xxx_timer6_hwmod = {
+ .name = "timer6",
+ .mpu_irqs = omap2_timer6_mpu_irqs,
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT6_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
+ },
},
- { }
-};
-
-/* l4_core -> usbhsotg */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_usbhsotg_hwmod,
- .clk = "l4_ick",
- .addr = omap3xxx_usbhsotg_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
- &omap3xxx_usbhsotg__l3,
-};
-
-static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
- &omap3xxx_l4_core__usbhsotg,
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap3xxx_timer_hwmod_class,
};
-static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
- {
- .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
- .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
+/* timer7 */
+static struct omap_hwmod omap3xxx_timer7_hwmod = {
+ .name = "timer7",
+ .mpu_irqs = omap2_timer7_mpu_irqs,
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT7_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
+ },
},
- { }
-};
-
-/* l4_core -> usbhsotg */
-static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &am35xx_usbhsotg_hwmod,
- .clk = "l4_ick",
- .addr = am35xx_usbhsotg_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
- &am35xx_usbhsotg__l3,
-};
-
-static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
- &am35xx_l4_core__usbhsotg,
-};
-/* Slave interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
- &omap3xxx_l3_main__l4_core,
-};
-
-/* L4 CORE */
-static struct omap_hwmod omap3xxx_l4_core_hwmod = {
- .name = "l4_core",
- .class = &l4_hwmod_class,
- .slaves = omap3xxx_l4_core_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* Slave interfaces on the L4_PER interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
- &omap3xxx_l3_main__l4_per,
-};
-
-/* L4 PER */
-static struct omap_hwmod omap3xxx_l4_per_hwmod = {
- .name = "l4_per",
- .class = &l4_hwmod_class,
- .slaves = omap3xxx_l4_per_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* Slave interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
- &omap3xxx_l4_core__l4_wkup,
-};
-
-/* L4 WKUP */
-static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
- .name = "l4_wkup",
- .class = &l4_hwmod_class,
- .slaves = omap3xxx_l4_wkup_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* Master interfaces on the MPU device */
-static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
- &omap3xxx_mpu__l3_main,
-};
-
-/* MPU */
-static struct omap_hwmod omap3xxx_mpu_hwmod = {
- .name = "mpu",
- .class = &mpu_hwmod_class,
- .main_clk = "arm_fck",
- .masters = omap3xxx_mpu_masters,
- .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
-};
-
-/*
- * IVA2_2 interface data
- */
-
-/* IVA2 <- L3 interface */
-static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
- .master = &omap3xxx_l3_main_hwmod,
- .slave = &omap3xxx_iva_hwmod,
- .clk = "iva2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
- &omap3xxx_l3__iva,
-};
-
-/*
- * IVA2 (IVA2)
- */
-
-static struct omap_hwmod omap3xxx_iva_hwmod = {
- .name = "iva",
- .class = &iva_hwmod_class,
- .masters = omap3xxx_iva_masters,
- .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
-};
-
-/* timer class */
-static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
- .name = "timer",
- .sysc = &omap3xxx_timer_1ms_sysc,
- .rev = OMAP_TIMER_IP_VERSION_1,
-};
-
-static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &omap3xxx_timer_sysc,
- .rev = OMAP_TIMER_IP_VERSION_1,
-};
-
-/* secure timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
- .timer_capability = OMAP_TIMER_SECURE,
-};
-
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &omap3xxx_timer_hwmod_class,
};
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_PWM,
+/* timer8 */
+static struct omap_hwmod omap3xxx_timer8_hwmod = {
+ .name = "timer8",
+ .mpu_irqs = omap2_timer8_mpu_irqs,
+ .main_clk = "gpt8_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT8_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
+ },
+ },
+ .dev_attr = &capability_pwm_dev_attr,
+ .class = &omap3xxx_timer_hwmod_class,
};
-/* timer1 */
-static struct omap_hwmod omap3xxx_timer1_hwmod;
+/* timer9 */
+static struct omap_hwmod omap3xxx_timer9_hwmod = {
+ .name = "timer9",
+ .mpu_irqs = omap2_timer9_mpu_irqs,
+ .main_clk = "gpt9_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT9_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
+ },
+ },
+ .dev_attr = &capability_pwm_dev_attr,
+ .class = &omap3xxx_timer_hwmod_class,
+};
-static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
- {
- .pa_start = 0x48318000,
- .pa_end = 0x48318000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
+/* timer10 */
+static struct omap_hwmod omap3xxx_timer10_hwmod = {
+ .name = "timer10",
+ .mpu_irqs = omap2_timer10_mpu_irqs,
+ .main_clk = "gpt10_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT10_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
+ },
},
- { }
+ .dev_attr = &capability_pwm_dev_attr,
+ .class = &omap3xxx_timer_1ms_hwmod_class,
};
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
- .master = &omap3xxx_l4_wkup_hwmod,
- .slave = &omap3xxx_timer1_hwmod,
- .clk = "gpt1_ick",
- .addr = omap3xxx_timer1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* timer11 */
+static struct omap_hwmod omap3xxx_timer11_hwmod = {
+ .name = "timer11",
+ .mpu_irqs = omap2_timer11_mpu_irqs,
+ .main_clk = "gpt11_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPT11_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
+ },
+ },
+ .dev_attr = &capability_pwm_dev_attr,
+ .class = &omap3xxx_timer_hwmod_class,
};
-/* timer1 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
- &omap3xxx_l4_wkup__timer1,
+/* timer12 */
+static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
+ { .irq = 95, },
+ { .irq = -1 }
};
-/* timer1 hwmod */
-static struct omap_hwmod omap3xxx_timer1_hwmod = {
- .name = "timer1",
- .mpu_irqs = omap2_timer1_mpu_irqs,
- .main_clk = "gpt1_fck",
+static struct omap_hwmod omap3xxx_timer12_hwmod = {
+ .name = "timer12",
+ .mpu_irqs = omap3xxx_timer12_mpu_irqs,
+ .main_clk = "gpt12_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT1_SHIFT,
+ .module_bit = OMAP3430_EN_GPT12_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap3xxx_timer1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
- .class = &omap3xxx_timer_1ms_hwmod_class,
+ .dev_attr = &capability_secure_dev_attr,
+ .class = &omap3xxx_timer_hwmod_class,
};
-/* timer2 */
-static struct omap_hwmod omap3xxx_timer2_hwmod;
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
-static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
- {
- .pa_start = 0x49032000,
- .pa_end = 0x49032000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
+static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_timer2_hwmod,
- .clk = "gpt2_ick",
- .addr = omap3xxx_timer2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x20,
+ .syss_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .clockact = CLOCKACT_TEST_ICLK,
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* timer2 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
- &omap3xxx_l4_per__timer2,
+static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+ .sysc = &omap3xxx_wd_timer_sysc,
+ .pre_shutdown = &omap2_wd_timer_disable,
+ .reset = &omap2_wd_timer_reset,
};
-/* timer2 hwmod */
-static struct omap_hwmod omap3xxx_timer2_hwmod = {
- .name = "timer2",
- .mpu_irqs = omap2_timer2_mpu_irqs,
- .main_clk = "gpt2_fck",
+static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
+ .name = "wd_timer2",
+ .class = &omap3xxx_wd_timer_hwmod_class,
+ .main_clk = "wdt2_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT2_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
+ .module_bit = OMAP3430_EN_WDT2_SHIFT,
+ .module_offs = WKUP_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap3xxx_timer2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
- .class = &omap3xxx_timer_1ms_hwmod_class,
+ /*
+ * XXX: Use software supervised mode, HW supervised smartidle seems to
+ * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
+ */
+ .flags = HWMOD_SWSUP_SIDLE,
};
-/* timer3 */
-static struct omap_hwmod omap3xxx_timer3_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
- {
- .pa_start = 0x49034000,
- .pa_end = 0x49034000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
+/* UART1 */
+static struct omap_hwmod omap3xxx_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = omap2_uart1_sdma_reqs,
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_UART1_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
+ },
},
- { }
-};
-
-/* l4_per -> timer3 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_timer3_hwmod,
- .clk = "gpt3_ick",
- .addr = omap3xxx_timer3_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer3 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
- &omap3xxx_l4_per__timer3,
+ .class = &omap2_uart_class,
};
-/* timer3 hwmod */
-static struct omap_hwmod omap3xxx_timer3_hwmod = {
- .name = "timer3",
- .mpu_irqs = omap2_timer3_mpu_irqs,
- .main_clk = "gpt3_fck",
+/* UART2 */
+static struct omap_hwmod omap3xxx_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = omap2_uart2_sdma_reqs,
+ .main_clk = "uart2_fck",
.prcm = {
.omap2 = {
+ .module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT3_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
+ .module_bit = OMAP3430_EN_UART2_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
+ .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap3xxx_timer3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
- .class = &omap3xxx_timer_hwmod_class,
+ .class = &omap2_uart_class,
};
-/* timer4 */
-static struct omap_hwmod omap3xxx_timer4_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
- {
- .pa_start = 0x49036000,
- .pa_end = 0x49036000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
+/* UART3 */
+static struct omap_hwmod omap3xxx_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = omap2_uart3_sdma_reqs,
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = OMAP3430_PER_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_UART3_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
+ },
},
- { }
+ .class = &omap2_uart_class,
};
-/* l4_per -> timer4 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_timer4_hwmod,
- .clk = "gpt4_ick",
- .addr = omap3xxx_timer4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* UART4 */
+static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
+ { .irq = INT_36XX_UART4_IRQ, },
+ { .irq = -1 }
};
-/* timer4 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
- &omap3xxx_l4_per__timer4,
+static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
+ { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
+ { .dma_req = -1 }
};
-/* timer4 hwmod */
-static struct omap_hwmod omap3xxx_timer4_hwmod = {
- .name = "timer4",
- .mpu_irqs = omap2_timer4_mpu_irqs,
- .main_clk = "gpt4_fck",
+static struct omap_hwmod omap36xx_uart4_hwmod = {
+ .name = "uart4",
+ .mpu_irqs = uart4_mpu_irqs,
+ .sdma_reqs = uart4_sdma_reqs,
+ .main_clk = "uart4_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT4_SHIFT,
.module_offs = OMAP3430_PER_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3630_EN_UART4_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
+ .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap3xxx_timer4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
- .class = &omap3xxx_timer_hwmod_class,
-};
-
-/* timer5 */
-static struct omap_hwmod omap3xxx_timer5_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
- {
- .pa_start = 0x49038000,
- .pa_end = 0x49038000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
+ .class = &omap2_uart_class,
};
-/* l4_per -> timer5 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_timer5_hwmod,
- .clk = "gpt5_ick",
- .addr = omap3xxx_timer5_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
+ { .irq = INT_35XX_UART4_IRQ, },
};
-/* timer5 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
- &omap3xxx_l4_per__timer5,
+static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
+ { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
+ { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
};
-/* timer5 hwmod */
-static struct omap_hwmod omap3xxx_timer5_hwmod = {
- .name = "timer5",
- .mpu_irqs = omap2_timer5_mpu_irqs,
- .main_clk = "gpt5_fck",
+static struct omap_hwmod am35xx_uart4_hwmod = {
+ .name = "uart4",
+ .mpu_irqs = am35xx_uart4_mpu_irqs,
+ .sdma_reqs = am35xx_uart4_sdma_reqs,
+ .main_clk = "uart4_fck",
.prcm = {
.omap2 = {
+ .module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT5_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
+ .module_bit = OMAP3430_EN_UART4_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
+ .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap3xxx_timer5_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
- .class = &omap3xxx_timer_hwmod_class,
+ .class = &omap2_uart_class,
};
-/* timer6 */
-static struct omap_hwmod omap3xxx_timer6_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
- {
- .pa_start = 0x4903A000,
- .pa_end = 0x4903A000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_1,
+ .reset = &omap_i2c_reset,
};
-/* l4_per -> timer6 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_timer6_hwmod,
- .clk = "gpt6_ick",
- .addr = omap3xxx_timer6_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
+ { .name = "dispc", .dma_req = 5 },
+ { .name = "dsi1", .dma_req = 74 },
+ { .dma_req = -1 }
};
-/* timer6 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
- &omap3xxx_l4_per__timer6,
+/* dss */
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+ /*
+ * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+ * driver does not use these clocks.
+ */
+ { .role = "sys_clk", .clk = "dss2_alwon_fck" },
+ { .role = "tv_clk", .clk = "dss_tv_fck" },
+ /* required only on OMAP3430 */
+ { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
};
-/* timer6 hwmod */
-static struct omap_hwmod omap3xxx_timer6_hwmod = {
- .name = "timer6",
- .mpu_irqs = omap2_timer6_mpu_irqs,
- .main_clk = "gpt6_fck",
+static struct omap_hwmod omap3430es1_dss_core_hwmod = {
+ .name = "dss_core",
+ .class = &omap2_dss_hwmod_class,
+ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
+ .sdma_reqs = omap3xxx_dss_sdma_chs,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT6_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
+ .module_bit = OMAP3430_EN_DSS1_SHIFT,
+ .module_offs = OMAP3430_DSS_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
+ .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap3xxx_timer6_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
- .class = &omap3xxx_timer_hwmod_class,
+ .opt_clks = dss_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+ .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
};
-/* timer7 */
-static struct omap_hwmod omap3xxx_timer7_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
- {
- .pa_start = 0x4903C000,
- .pa_end = 0x4903C000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod omap3xxx_dss_core_hwmod = {
+ .name = "dss_core",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .class = &omap2_dss_hwmod_class,
+ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
+ .sdma_reqs = omap3xxx_dss_sdma_chs,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_DSS1_SHIFT,
+ .module_offs = OMAP3430_DSS_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
+ .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
+ },
},
- { }
+ .opt_clks = dss_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
};
-/* l4_per -> timer7 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_timer7_hwmod,
- .clk = "gpt7_ick",
- .addr = omap3xxx_timer7_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSC_HAS_ENAWAKEUP),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* timer7 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
- &omap3xxx_l4_per__timer7,
+static struct omap_hwmod_class omap3_dispc_hwmod_class = {
+ .name = "dispc",
+ .sysc = &omap3_dispc_sysc,
};
-/* timer7 hwmod */
-static struct omap_hwmod omap3xxx_timer7_hwmod = {
- .name = "timer7",
- .mpu_irqs = omap2_timer7_mpu_irqs,
- .main_clk = "gpt7_fck",
+static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap3_dispc_hwmod_class,
+ .mpu_irqs = omap2_dispc_irqs,
+ .main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT7_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
+ .module_bit = OMAP3430_EN_DSS1_SHIFT,
+ .module_offs = OMAP3430_DSS_MOD,
},
},
- .dev_attr = &capability_alwon_dev_attr,
- .slaves = omap3xxx_timer7_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
- .class = &omap3xxx_timer_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
+ .dev_attr = &omap2_3_dss_dispc_dev_attr
};
-/* timer8 */
-static struct omap_hwmod omap3xxx_timer8_hwmod;
+/*
+ * 'dsi' class
+ * display serial interface controller
+ */
-static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
- {
- .pa_start = 0x4903E000,
- .pa_end = 0x4903E000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
+static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
+ .name = "dsi",
};
-/* l4_per -> timer8 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_timer8_hwmod,
- .clk = "gpt8_ick",
- .addr = omap3xxx_timer8_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
+ { .irq = 25 },
+ { .irq = -1 }
};
-/* timer8 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
- &omap3xxx_l4_per__timer8,
+/* dss_dsi1 */
+static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
+ { .role = "sys_clk", .clk = "dss2_alwon_fck" },
};
-/* timer8 hwmod */
-static struct omap_hwmod omap3xxx_timer8_hwmod = {
- .name = "timer8",
- .mpu_irqs = omap2_timer8_mpu_irqs,
- .main_clk = "gpt8_fck",
+static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
+ .name = "dss_dsi1",
+ .class = &omap3xxx_dsi_hwmod_class,
+ .mpu_irqs = omap3xxx_dsi1_irqs,
+ .main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT8_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
+ .module_bit = OMAP3430_EN_DSS1_SHIFT,
+ .module_offs = OMAP3430_DSS_MOD,
},
},
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap3xxx_timer8_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
- .class = &omap3xxx_timer_hwmod_class,
-};
-
-/* timer9 */
-static struct omap_hwmod omap3xxx_timer9_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
- {
- .pa_start = 0x49040000,
- .pa_end = 0x49040000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> timer9 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_timer9_hwmod,
- .clk = "gpt9_ick",
- .addr = omap3xxx_timer9_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .opt_clks = dss_dsi1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
+ .flags = HWMOD_NO_IDLEST,
};
-/* timer9 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
- &omap3xxx_l4_per__timer9,
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+ { .role = "ick", .clk = "dss_ick" },
};
-/* timer9 hwmod */
-static struct omap_hwmod omap3xxx_timer9_hwmod = {
- .name = "timer9",
- .mpu_irqs = omap2_timer9_mpu_irqs,
- .main_clk = "gpt9_fck",
+static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
+ .name = "dss_rfbi",
+ .class = &omap2_rfbi_hwmod_class,
+ .main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT9_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
+ .module_bit = OMAP3430_EN_DSS1_SHIFT,
+ .module_offs = OMAP3430_DSS_MOD,
},
},
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap3xxx_timer9_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
- .class = &omap3xxx_timer_hwmod_class,
+ .opt_clks = dss_rfbi_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
+ .flags = HWMOD_NO_IDLEST,
};
-/* timer10 */
-static struct omap_hwmod omap3xxx_timer10_hwmod;
+static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
+ /* required only on OMAP3430 */
+ { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
+};
-/* l4_core -> timer10 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_timer10_hwmod,
- .clk = "gpt10_ick",
- .addr = omap2_timer10_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
+ .name = "dss_venc",
+ .class = &omap2_venc_hwmod_class,
+ .main_clk = "dss_tv_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_DSS1_SHIFT,
+ .module_offs = OMAP3430_DSS_MOD,
+ },
+ },
+ .opt_clks = dss_venc_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
+ .flags = HWMOD_NO_IDLEST,
};
-/* timer10 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
- &omap3xxx_l4_core__timer10,
+/* I2C1 */
+static struct omap_i2c_dev_attr i2c1_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+ OMAP_I2C_FLAG_BUS_SHIFT_2,
};
-/* timer10 hwmod */
-static struct omap_hwmod omap3xxx_timer10_hwmod = {
- .name = "timer10",
- .mpu_irqs = omap2_timer10_mpu_irqs,
- .main_clk = "gpt10_fck",
+static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+ .name = "i2c1",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = omap2_i2c1_sdma_reqs,
+ .main_clk = "i2c1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT10_SHIFT,
.module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_I2C1_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap3xxx_timer10_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
- .class = &omap3xxx_timer_1ms_hwmod_class,
-};
-
-/* timer11 */
-static struct omap_hwmod omap3xxx_timer11_hwmod;
-
-/* l4_core -> timer11 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_timer11_hwmod,
- .clk = "gpt11_ick",
- .addr = omap2_timer11_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .class = &i2c_class,
+ .dev_attr = &i2c1_dev_attr,
};
-/* timer11 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
- &omap3xxx_l4_core__timer11,
+/* I2C2 */
+static struct omap_i2c_dev_attr i2c2_dev_attr = {
+ .fifo_depth = 8, /* bytes */
+ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+ OMAP_I2C_FLAG_BUS_SHIFT_2,
};
-/* timer11 hwmod */
-static struct omap_hwmod omap3xxx_timer11_hwmod = {
- .name = "timer11",
- .mpu_irqs = omap2_timer11_mpu_irqs,
- .main_clk = "gpt11_fck",
+static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+ .name = "i2c2",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = omap2_i2c2_sdma_reqs,
+ .main_clk = "i2c2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT11_SHIFT,
.module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_I2C2_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
- .slaves = omap3xxx_timer11_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
- .class = &omap3xxx_timer_hwmod_class,
-};
-
-/* timer12*/
-static struct omap_hwmod omap3xxx_timer12_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
- { .irq = 95, },
- { .irq = -1 }
+ .class = &i2c_class,
+ .dev_attr = &i2c2_dev_attr,
};
-static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
- {
- .pa_start = 0x48304000,
- .pa_end = 0x48304000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
+/* I2C3 */
+static struct omap_i2c_dev_attr i2c3_dev_attr = {
+ .fifo_depth = 64, /* bytes */
+ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+ OMAP_I2C_FLAG_BUS_SHIFT_2,
};
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_timer12_hwmod,
- .clk = "gpt12_ick",
- .addr = omap3xxx_timer12_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+ { .irq = INT_34XX_I2C3_IRQ, },
+ { .irq = -1 }
};
-/* timer12 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
- &omap3xxx_l4_core__timer12,
+static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
+ { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
+ { .dma_req = -1 }
};
-/* timer12 hwmod */
-static struct omap_hwmod omap3xxx_timer12_hwmod = {
- .name = "timer12",
- .mpu_irqs = omap3xxx_timer12_mpu_irqs,
- .main_clk = "gpt12_fck",
+static struct omap_hwmod omap3xxx_i2c3_hwmod = {
+ .name = "i2c3",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = i2c3_mpu_irqs,
+ .sdma_reqs = i2c3_sdma_reqs,
+ .main_clk = "i2c3_fck",
.prcm = {
.omap2 = {
+ .module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT12_SHIFT,
- .module_offs = WKUP_MOD,
+ .module_bit = OMAP3430_EN_I2C3_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
},
},
- .dev_attr = &capability_secure_dev_attr,
- .slaves = omap3xxx_timer12_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
- .class = &omap3xxx_timer_hwmod_class,
-};
-
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
- {
- .pa_start = 0x48314000,
- .pa_end = 0x4831407f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
- .master = &omap3xxx_l4_wkup_hwmod,
- .slave = &omap3xxx_wd_timer2_hwmod,
- .clk = "wdt2_ick",
- .addr = omap3xxx_wd_timer2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .class = &i2c_class,
+ .dev_attr = &i2c3_dev_attr,
};
/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
+ * 'gpio' class
+ * general purpose io module
*/
-static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
+static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
-/* I2C common */
-static struct omap_hwmod_class_sysconfig i2c_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x20,
- .syss_offs = 0x10,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .clockact = CLOCKACT_TEST_ICLK,
- .sysc_fields = &omap_hwmod_sysc_type1,
+static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &omap3xxx_gpio_sysc,
+ .rev = 1,
};
-static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &omap3xxx_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable
+/* gpio_dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbck", },
+};
+
+static struct omap_hwmod omap3xxx_gpio1_hwmod = {
+ .name = "gpio1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2_gpio1_irqs,
+ .main_clk = "gpio1_ick",
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPIO1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
+ },
+ },
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbck", },
+};
+
+static struct omap_hwmod omap3xxx_gpio2_hwmod = {
+ .name = "gpio2",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2_gpio2_irqs,
+ .main_clk = "gpio2_ick",
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_GPIO2_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
+ },
+ },
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
};
-/* wd_timer2 */
-static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
- &omap3xxx_l4_wkup__wd_timer2,
+/* gpio3 */
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbck", },
};
-static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
- .name = "wd_timer2",
- .class = &omap3xxx_wd_timer_hwmod_class,
- .main_clk = "wdt2_fck",
+static struct omap_hwmod omap3xxx_gpio3_hwmod = {
+ .name = "gpio3",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2_gpio3_irqs,
+ .main_clk = "gpio3_ick",
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_WDT2_SHIFT,
- .module_offs = WKUP_MOD,
+ .module_bit = OMAP3430_EN_GPIO3_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
},
},
- .slaves = omap3xxx_wd_timer2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
- /*
- * XXX: Use software supervised mode, HW supervised smartidle seems to
- * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
- */
- .flags = HWMOD_SWSUP_SIDLE,
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
};
-/* UART1 */
-
-static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
- &omap3_l4_core__uart1,
+/* gpio4 */
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio4_dbck", },
};
-static struct omap_hwmod omap3xxx_uart1_hwmod = {
- .name = "uart1",
- .mpu_irqs = omap2_uart1_mpu_irqs,
- .sdma_reqs = omap2_uart1_sdma_reqs,
- .main_clk = "uart1_fck",
+static struct omap_hwmod omap3xxx_gpio4_hwmod = {
+ .name = "gpio4",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap2_gpio4_irqs,
+ .main_clk = "gpio4_ick",
+ .opt_clks = gpio4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
.prcm = {
.omap2 = {
- .module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_UART1_SHIFT,
+ .module_bit = OMAP3430_EN_GPIO4_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
},
},
- .slaves = omap3xxx_uart1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
- .class = &omap2_uart_class,
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
};
-/* UART2 */
+/* gpio5 */
+static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
+ { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
+ { .irq = -1 }
+};
-static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
- &omap3_l4_core__uart2,
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio5_dbck", },
};
-static struct omap_hwmod omap3xxx_uart2_hwmod = {
- .name = "uart2",
- .mpu_irqs = omap2_uart2_mpu_irqs,
- .sdma_reqs = omap2_uart2_sdma_reqs,
- .main_clk = "uart2_fck",
+static struct omap_hwmod omap3xxx_gpio5_hwmod = {
+ .name = "gpio5",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap3xxx_gpio5_irqs,
+ .main_clk = "gpio5_ick",
+ .opt_clks = gpio5_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
.prcm = {
.omap2 = {
- .module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_UART2_SHIFT,
+ .module_bit = OMAP3430_EN_GPIO5_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
},
},
- .slaves = omap3xxx_uart2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
- .class = &omap2_uart_class,
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
};
-/* UART3 */
+/* gpio6 */
+static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
+ { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
+ { .irq = -1 }
+};
-static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
- &omap3_l4_per__uart3,
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio6_dbck", },
};
-static struct omap_hwmod omap3xxx_uart3_hwmod = {
- .name = "uart3",
- .mpu_irqs = omap2_uart3_mpu_irqs,
- .sdma_reqs = omap2_uart3_sdma_reqs,
- .main_clk = "uart3_fck",
+static struct omap_hwmod omap3xxx_gpio6_hwmod = {
+ .name = "gpio6",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = omap3xxx_gpio6_irqs,
+ .main_clk = "gpio6_ick",
+ .opt_clks = gpio6_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
.prcm = {
.omap2 = {
- .module_offs = OMAP3430_PER_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_UART3_SHIFT,
+ .module_bit = OMAP3430_EN_GPIO6_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
},
},
- .slaves = omap3xxx_uart3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
- .class = &omap2_uart_class,
+ .class = &omap3xxx_gpio_hwmod_class,
+ .dev_attr = &gpio_dev_attr,
};
-/* UART4 */
-
-static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
- { .irq = INT_36XX_UART4_IRQ, },
- { .irq = -1 }
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+ IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+ .lch_count = 32,
};
-static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
- { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
- { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
- { .dma_req = -1 }
+static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x002c,
+ .syss_offs = 0x0028,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
- &omap3_l4_per__uart4,
+static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
+ .name = "dma",
+ .sysc = &omap3xxx_dma_sysc,
};
-static struct omap_hwmod omap3xxx_uart4_hwmod = {
- .name = "uart4",
- .mpu_irqs = uart4_mpu_irqs,
- .sdma_reqs = uart4_sdma_reqs,
- .main_clk = "uart4_fck",
- .prcm = {
+/* dma_system */
+static struct omap_hwmod omap3xxx_dma_system_hwmod = {
+ .name = "dma",
+ .class = &omap3xxx_dma_hwmod_class,
+ .mpu_irqs = omap2_dma_system_irqs,
+ .main_clk = "core_l3_ick",
+ .prcm = {
.omap2 = {
- .module_offs = OMAP3430_PER_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3630_EN_UART4_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_ST_SDMA_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
},
},
- .slaves = omap3xxx_uart4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
- .class = &omap2_uart_class,
+ .dev_attr = &dma_dev_attr,
+ .flags = HWMOD_NO_IDLEST,
};
-static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
- { .irq = INT_35XX_UART4_IRQ, },
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
+ .sysc_offs = 0x008c,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ .clockact = 0x2,
};
-static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
- { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
- { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
+static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
+ .name = "mcbsp",
+ .sysc = &omap3xxx_mcbsp_sysc,
+ .rev = MCBSP_CONFIG_TYPE3,
};
-static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
- &am35xx_l4_core__uart4,
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
+ { .name = "common", .irq = 16 },
+ { .name = "tx", .irq = 59 },
+ { .name = "rx", .irq = 60 },
+ { .irq = -1 }
};
-static struct omap_hwmod am35xx_uart4_hwmod = {
- .name = "uart4",
- .mpu_irqs = am35xx_uart4_mpu_irqs,
- .sdma_reqs = am35xx_uart4_sdma_reqs,
- .main_clk = "uart4_fck",
- .prcm = {
+static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp1_irqs,
+ .sdma_reqs = omap2_mcbsp1_sdma_reqs,
+ .main_clk = "mcbsp1_fck",
+ .prcm = {
.omap2 = {
- .module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_UART4_SHIFT,
+ .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
+ .module_offs = CORE_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
},
},
- .slaves = am35xx_uart4_slaves,
- .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves),
- .class = &omap2_uart_class,
};
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
+ { .name = "common", .irq = 17 },
+ { .name = "tx", .irq = 62 },
+ { .name = "rx", .irq = 63 },
+ { .irq = -1 }
+};
-static struct omap_hwmod_class i2c_class = {
- .name = "i2c",
- .sysc = &i2c_sysc,
- .rev = OMAP_I2C_IP_VERSION_1,
- .reset = &omap_i2c_reset,
+static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
+ .sidetone = "mcbsp2_sidetone",
};
-static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
- { .name = "dispc", .dma_req = 5 },
- { .name = "dsi1", .dma_req = 74 },
- { .dma_req = -1 }
+static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp2_irqs,
+ .sdma_reqs = omap2_mcbsp2_sdma_reqs,
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
+ },
+ },
+ .dev_attr = &omap34xx_mcbsp2_dev_attr,
};
-/* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
- &omap3xxx_dss__l3,
+/* mcbsp3 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
+ { .name = "common", .irq = 22 },
+ { .name = "tx", .irq = 89 },
+ { .name = "rx", .irq = 90 },
+ { .irq = -1 }
};
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3430es1_dss_core_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_addrs,
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
- .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
- .flags = OMAP_FIREWALL_L4,
- }
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
+ .sidetone = "mcbsp3_sidetone",
};
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_dss_core_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_addrs,
- .fw = {
+static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
+ .name = "mcbsp3",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp3_irqs,
+ .sdma_reqs = omap2_mcbsp3_sdma_reqs,
+ .main_clk = "mcbsp3_fck",
+ .prcm = {
.omap2 = {
- .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
- .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
- .flags = OMAP_FIREWALL_L4,
- }
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
+ },
},
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
- &omap3430es1_l4_core__dss,
+ .dev_attr = &omap34xx_mcbsp3_dev_attr,
};
-static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
- &omap3xxx_l4_core__dss,
+/* mcbsp4 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
+ { .name = "common", .irq = 23 },
+ { .name = "tx", .irq = 54 },
+ { .name = "rx", .irq = 55 },
+ { .irq = -1 }
};
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- /*
- * The DSS HW needs all DSS clocks enabled during reset. The dss_core
- * driver does not use these clocks.
- */
- { .role = "sys_clk", .clk = "dss2_alwon_fck" },
- { .role = "tv_clk", .clk = "dss_tv_fck" },
- /* required only on OMAP3430 */
- { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
+static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
+ { .name = "rx", .dma_req = 20 },
+ { .name = "tx", .dma_req = 19 },
+ { .dma_req = -1 }
};
-static struct omap_hwmod omap3430es1_dss_core_hwmod = {
- .name = "dss_core",
- .class = &omap2_dss_hwmod_class,
- .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
- .sdma_reqs = omap3xxx_dss_sdma_chs,
+static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
+ .name = "mcbsp4",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp4_irqs,
+ .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
+ .main_clk = "mcbsp4_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
- .module_offs = OMAP3430_DSS_MOD,
+ .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
- .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
},
},
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
- .slaves = omap3430es1_dss_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
- .masters = omap3xxx_dss_masters,
- .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
- .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
};
-static struct omap_hwmod omap3xxx_dss_core_hwmod = {
- .name = "dss_core",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .class = &omap2_dss_hwmod_class,
- .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
- .sdma_reqs = omap3xxx_dss_sdma_chs,
+/* mcbsp5 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
+ { .name = "common", .irq = 27 },
+ { .name = "tx", .irq = 81 },
+ { .name = "rx", .irq = 82 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
+ { .name = "rx", .dma_req = 22 },
+ { .name = "tx", .dma_req = 21 },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
+ .name = "mcbsp5",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp5_irqs,
+ .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
+ .main_clk = "mcbsp5_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
- .module_offs = OMAP3430_DSS_MOD,
+ .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
+ .module_offs = CORE_MOD,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
- .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
},
},
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
- .slaves = omap3xxx_dss_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
- .masters = omap3xxx_dss_masters,
- .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
};
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
- .rev_offs = 0x0000,
+/* 'mcbsp sidetone' class */
+static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
.sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSC_HAS_ENAWAKEUP),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_flags = SYSC_HAS_AUTOIDLE,
.sysc_fields = &omap_hwmod_sysc_type1,
};
-static struct omap_hwmod_class omap3_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap3_dispc_sysc,
+static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
+ .name = "mcbsp_sidetone",
+ .sysc = &omap3xxx_mcbsp_sidetone_sysc,
};
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_dss_dispc_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_dispc_addrs,
- .fw = {
+/* mcbsp2_sidetone */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
+ { .name = "irq", .irq = 4 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
+ .name = "mcbsp2_sidetone",
+ .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
+ .main_clk = "mcbsp2_fck",
+ .prcm = {
.omap2 = {
- .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
- .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
- .flags = OMAP_FIREWALL_L4,
- }
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
+ },
},
- .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
- &omap3xxx_l4_core__dss_dispc,
+/* mcbsp3_sidetone */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
+ { .name = "irq", .irq = 5 },
+ { .irq = -1 }
};
-static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &omap3_dispc_hwmod_class,
- .mpu_irqs = omap2_dispc_irqs,
- .main_clk = "dss1_alwon_fck",
+static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
+ .name = "mcbsp3_sidetone",
+ .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
+ .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
+ .main_clk = "mcbsp3_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
- .module_offs = OMAP3430_DSS_MOD,
+ .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
+ .module_offs = OMAP3430_PER_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
},
},
- .slaves = omap3xxx_dss_dispc_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
- .flags = HWMOD_NO_IDLEST,
- .dev_attr = &omap2_3_dss_dispc_dev_attr
};
-/*
- * 'dsi' class
- * display serial interface controller
- */
+/* SR common */
+static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
+ .clkact_shift = 20,
+};
-static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
- .name = "dsi",
+static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
+ .sysc_offs = 0x24,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
+ .clockact = CLOCKACT_TEST_ICLK,
+ .sysc_fields = &omap34xx_sr_sysc_fields,
};
-static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
- { .irq = 25 },
- { .irq = -1 }
+static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
+ .name = "smartreflex",
+ .sysc = &omap34xx_sr_sysc,
+ .rev = 1,
};
-/* dss_dsi1 */
-static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
- {
- .pa_start = 0x4804FC00,
- .pa_end = 0x4804FFFF,
- .flags = ADDR_TYPE_RT
- },
- { }
+static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
+ .sidle_shift = 24,
+ .enwkup_shift = 26,
};
-/* l4_core -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_dss_dsi1_hwmod,
- .clk = "dss_ick",
- .addr = omap3xxx_dss_dsi1_addrs,
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
- .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
- .flags = OMAP_FIREWALL_L4,
- }
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
+ .sysc_offs = 0x38,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_NO_CACHE),
+ .sysc_fields = &omap36xx_sr_sysc_fields,
};
-/* dss_dsi1 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
- &omap3xxx_l4_core__dss_dsi1,
+static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
+ .name = "smartreflex",
+ .sysc = &omap36xx_sr_sysc,
+ .rev = 2,
};
-static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss2_alwon_fck" },
+/* SR1 */
+static struct omap_smartreflex_dev_attr sr1_dev_attr = {
+ .sensor_voltdm_name = "mpu_iva",
+};
+
+static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
+ { .irq = 18 },
+ { .irq = -1 }
};
-static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
- .name = "dss_dsi1",
- .class = &omap3xxx_dsi_hwmod_class,
- .mpu_irqs = omap3xxx_dsi1_irqs,
- .main_clk = "dss1_alwon_fck",
+static struct omap_hwmod omap34xx_sr1_hwmod = {
+ .name = "sr1",
+ .class = &omap34xx_smartreflex_hwmod_class,
+ .main_clk = "sr1_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
- .module_offs = OMAP3430_DSS_MOD,
+ .module_bit = OMAP3430_EN_SR1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
},
},
- .opt_clks = dss_dsi1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
- .slaves = omap3xxx_dss_dsi1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
- .flags = HWMOD_NO_IDLEST,
+ .dev_attr = &sr1_dev_attr,
+ .mpu_irqs = omap3_smartreflex_mpu_irqs,
+ .flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_dss_rfbi_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_rfbi_addrs,
- .fw = {
+static struct omap_hwmod omap36xx_sr1_hwmod = {
+ .name = "sr1",
+ .class = &omap36xx_smartreflex_hwmod_class,
+ .main_clk = "sr1_fck",
+ .prcm = {
.omap2 = {
- .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
- .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
- .flags = OMAP_FIREWALL_L4,
- }
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_SR1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
+ },
},
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .dev_attr = &sr1_dev_attr,
+ .mpu_irqs = omap3_smartreflex_mpu_irqs,
};
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
- &omap3xxx_l4_core__dss_rfbi,
+/* SR2 */
+static struct omap_smartreflex_dev_attr sr2_dev_attr = {
+ .sensor_voltdm_name = "core",
};
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
- { .role = "ick", .clk = "dss_ick" },
+static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
+ { .irq = 19 },
+ { .irq = -1 }
};
-static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap2_rfbi_hwmod_class,
- .main_clk = "dss1_alwon_fck",
+static struct omap_hwmod omap34xx_sr2_hwmod = {
+ .name = "sr2",
+ .class = &omap34xx_smartreflex_hwmod_class,
+ .main_clk = "sr2_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
- .module_offs = OMAP3430_DSS_MOD,
+ .module_bit = OMAP3430_EN_SR2_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
},
},
- .opt_clks = dss_rfbi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
- .slaves = omap3xxx_dss_rfbi_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
- .flags = HWMOD_NO_IDLEST,
+ .dev_attr = &sr2_dev_attr,
+ .mpu_irqs = omap3_smartreflex_core_irqs,
+ .flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_dss_venc_hwmod,
- .clk = "dss_ick",
- .addr = omap2_dss_venc_addrs,
- .fw = {
+static struct omap_hwmod omap36xx_sr2_hwmod = {
+ .name = "sr2",
+ .class = &omap36xx_smartreflex_hwmod_class,
+ .main_clk = "sr2_fck",
+ .prcm = {
.omap2 = {
- .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
- .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
- .flags = OMAP_FIREWALL_L4,
- }
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_SR2_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
+ },
},
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .dev_attr = &sr2_dev_attr,
+ .mpu_irqs = omap3_smartreflex_core_irqs,
};
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
- &omap3xxx_l4_core__dss_venc,
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
- /* required only on OMAP3430 */
- { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
+static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &omap3xxx_mailbox_sysc,
};
-static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
- .name = "dss_venc",
- .class = &omap2_venc_hwmod_class,
- .main_clk = "dss_tv_fck",
+static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
+ { .irq = 26 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap3xxx_mailbox_hwmod_class,
+ .mpu_irqs = omap3xxx_mailbox_irqs,
+ .main_clk = "mailboxes_ick",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
- .module_offs = OMAP3430_DSS_MOD,
+ .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
},
},
- .opt_clks = dss_venc_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
- .slaves = omap3xxx_dss_venc_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
- .flags = HWMOD_NO_IDLEST,
};
-/* I2C1 */
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
-static struct omap_i2c_dev_attr i2c1_dev_attr = {
- .fifo_depth = 8, /* bytes */
- .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
- OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
- OMAP_I2C_FLAG_BUS_SHIFT_2,
+static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
- &omap3_l4_core__i2c1,
+static struct omap_hwmod_class omap34xx_mcspi_class = {
+ .name = "mcspi",
+ .sysc = &omap34xx_mcspi_sysc,
+ .rev = OMAP3_MCSPI_REV,
};
-static struct omap_hwmod omap3xxx_i2c1_hwmod = {
- .name = "i2c1",
- .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .mpu_irqs = omap2_i2c1_mpu_irqs,
- .sdma_reqs = omap2_i2c1_sdma_reqs,
- .main_clk = "i2c1_fck",
+/* mcspi1 */
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+ .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap34xx_mcspi1 = {
+ .name = "mcspi1",
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap2_mcspi1_sdma_reqs,
+ .main_clk = "mcspi1_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_I2C1_SHIFT,
+ .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
},
},
- .slaves = omap3xxx_i2c1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
- .class = &i2c_class,
- .dev_attr = &i2c1_dev_attr,
-};
-
-/* I2C2 */
-
-static struct omap_i2c_dev_attr i2c2_dev_attr = {
- .fifo_depth = 8, /* bytes */
- .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
- OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
- OMAP_I2C_FLAG_BUS_SHIFT_2,
+ .class = &omap34xx_mcspi_class,
+ .dev_attr = &omap_mcspi1_dev_attr,
};
-static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
- &omap3_l4_core__i2c2,
+/* mcspi2 */
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+ .num_chipselect = 2,
};
-static struct omap_hwmod omap3xxx_i2c2_hwmod = {
- .name = "i2c2",
- .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .mpu_irqs = omap2_i2c2_mpu_irqs,
- .sdma_reqs = omap2_i2c2_sdma_reqs,
- .main_clk = "i2c2_fck",
+static struct omap_hwmod omap34xx_mcspi2 = {
+ .name = "mcspi2",
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap2_mcspi2_sdma_reqs,
+ .main_clk = "mcspi2_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_I2C2_SHIFT,
+ .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
},
},
- .slaves = omap3xxx_i2c2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
- .class = &i2c_class,
- .dev_attr = &i2c2_dev_attr,
+ .class = &omap34xx_mcspi_class,
+ .dev_attr = &omap_mcspi2_dev_attr,
};
-/* I2C3 */
+/* mcspi3 */
+static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
+ { .name = "irq", .irq = 91 }, /* 91 */
+ { .irq = -1 }
+};
-static struct omap_i2c_dev_attr i2c3_dev_attr = {
- .fifo_depth = 64, /* bytes */
- .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
- OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
- OMAP_I2C_FLAG_BUS_SHIFT_2,
+static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 15 },
+ { .name = "rx0", .dma_req = 16 },
+ { .name = "tx1", .dma_req = 23 },
+ { .name = "rx1", .dma_req = 24 },
+ { .dma_req = -1 }
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+ .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap34xx_mcspi3 = {
+ .name = "mcspi3",
+ .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
+ .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
+ .main_clk = "mcspi3_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
+ },
+ },
+ .class = &omap34xx_mcspi_class,
+ .dev_attr = &omap_mcspi3_dev_attr,
};
-static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
- { .irq = INT_34XX_I2C3_IRQ, },
+/* mcspi4 */
+static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
+ { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
{ .irq = -1 }
};
-static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
- { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
- { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
+static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
+ { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
{ .dma_req = -1 }
};
-static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
- &omap3_l4_core__i2c3,
+static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
+ .num_chipselect = 1,
};
-static struct omap_hwmod omap3xxx_i2c3_hwmod = {
- .name = "i2c3",
- .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .mpu_irqs = i2c3_mpu_irqs,
- .sdma_reqs = i2c3_sdma_reqs,
- .main_clk = "i2c3_fck",
+static struct omap_hwmod omap34xx_mcspi4 = {
+ .name = "mcspi4",
+ .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
+ .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
+ .main_clk = "mcspi4_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_I2C3_SHIFT,
+ .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
},
},
- .slaves = omap3xxx_i2c3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
- .class = &i2c_class,
- .dev_attr = &i2c3_dev_attr,
+ .class = &omap34xx_mcspi_class,
+ .dev_attr = &omap_mcspi4_dev_attr,
};
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
- {
- .pa_start = 0x48310000,
- .pa_end = 0x483101ff,
- .flags = ADDR_TYPE_RT
- },
- { }
+/* usbhsotg */
+static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
+ .rev_offs = 0x0400,
+ .sysc_offs = 0x0404,
+ .syss_offs = 0x0408,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
- .master = &omap3xxx_l4_wkup_hwmod,
- .slave = &omap3xxx_gpio1_hwmod,
- .addr = omap3xxx_gpio1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class usbotg_class = {
+ .name = "usbotg",
+ .sysc = &omap3xxx_usbhsotg_sysc,
};
-/* l4_per -> gpio2 */
-static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
- {
- .pa_start = 0x49050000,
- .pa_end = 0x490501ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_gpio2_hwmod,
- .addr = omap3xxx_gpio2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ { .name = "mc", .irq = 92 },
+ { .name = "dma", .irq = 93 },
+ { .irq = -1 }
};
-/* l4_per -> gpio3 */
-static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
- {
- .pa_start = 0x49052000,
- .pa_end = 0x490521ff,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
+ .name = "usb_otg_hs",
+ .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
+ .main_clk = "hsotgusb_ick",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
+ .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
+ },
},
- { }
-};
+ .class = &usbotg_class,
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_gpio3_hwmod,
- .addr = omap3xxx_gpio3_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ /*
+ * Erratum ID: i479 idle_req / idle_ack mechanism potentially
+ * broken when autoidle is enabled
+ * workaround is to disable the autoidle bit at module level.
+ */
+ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
+ | HWMOD_SWSUP_MSTANDBY,
};
-/* l4_per -> gpio4 */
-static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
- {
- .pa_start = 0x49054000,
- .pa_end = 0x490541ff,
- .flags = ADDR_TYPE_RT
- },
- { }
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
+
+ { .name = "mc", .irq = 71 },
+ { .irq = -1 }
};
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_gpio4_hwmod,
- .addr = omap3xxx_gpio4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class am35xx_usbotg_class = {
+ .name = "am35xx_usbotg",
+ .sysc = NULL,
};
-/* l4_per -> gpio5 */
-static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
- {
- .pa_start = 0x49056000,
- .pa_end = 0x490561ff,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod am35xx_usbhsotg_hwmod = {
+ .name = "am35x_otg_hs",
+ .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
+ .main_clk = NULL,
+ .prcm = {
+ .omap2 = {
+ },
},
- { }
+ .class = &am35xx_usbotg_class,
};
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_gpio5_hwmod,
- .addr = omap3xxx_gpio5_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* MMC/SD/SDIO common */
+static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
+ .rev_offs = 0x1fc,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* l4_per -> gpio6 */
-static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
- {
- .pa_start = 0x49058000,
- .pa_end = 0x490581ff,
- .flags = ADDR_TYPE_RT
- },
- { }
+static struct omap_hwmod_class omap34xx_mmc_class = {
+ .name = "mmc",
+ .sysc = &omap34xx_mmc_sysc,
};
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_gpio6_hwmod,
- .addr = omap3xxx_gpio6_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
+/* MMC/SD/SDIO1 */
-/*
- * 'gpio' class
- * general purpose io module
- */
+static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
+ { .irq = 83, },
+ { .irq = -1 }
+};
-static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
+static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 61, },
+ { .name = "rx", .dma_req = 62, },
+ { .dma_req = -1 }
};
-static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
- .name = "gpio",
- .sysc = &omap3xxx_gpio_sysc,
- .rev = 1,
+static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
+ { .role = "dbck", .clk = "omap_32k_fck", },
};
-/* gpio_dev_attr*/
-static struct omap_gpio_dev_attr gpio_dev_attr = {
- .bank_width = 32,
- .dbck_flag = true,
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};
-/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio1_dbck", },
+/* See 35xx errata 2.1.1.128 in SPRZ278F */
+static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
+ .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
+ OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
};
-static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
- &omap3xxx_l4_wkup__gpio1,
+static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
+ .name = "mmc1",
+ .mpu_irqs = omap34xx_mmc1_mpu_irqs,
+ .sdma_reqs = omap34xx_mmc1_sdma_reqs,
+ .opt_clks = omap34xx_mmc1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
+ .main_clk = "mmchs1_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_MMC1_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
+ },
+ },
+ .dev_attr = &mmc1_pre_es3_dev_attr,
+ .class = &omap34xx_mmc_class,
};
-static struct omap_hwmod omap3xxx_gpio1_hwmod = {
- .name = "gpio1",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio1_irqs,
- .main_clk = "gpio1_ick",
- .opt_clks = gpio1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
+ .name = "mmc1",
+ .mpu_irqs = omap34xx_mmc1_mpu_irqs,
+ .sdma_reqs = omap34xx_mmc1_sdma_reqs,
+ .opt_clks = omap34xx_mmc1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
+ .main_clk = "mmchs1_fck",
.prcm = {
.omap2 = {
+ .module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO1_SHIFT,
- .module_offs = WKUP_MOD,
+ .module_bit = OMAP3430_EN_MMC1_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
},
},
- .slaves = omap3xxx_gpio1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
- .class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
+ .dev_attr = &mmc1_dev_attr,
+ .class = &omap34xx_mmc_class,
};
-/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio2_dbck", },
-};
+/* MMC/SD/SDIO2 */
-static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
- &omap3xxx_l4_per__gpio2,
+static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
+ { .irq = INT_24XX_MMC2_IRQ, },
+ { .irq = -1 }
};
-static struct omap_hwmod omap3xxx_gpio2_hwmod = {
- .name = "gpio2",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio2_irqs,
- .main_clk = "gpio2_ick",
- .opt_clks = gpio2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO2_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
- },
- },
- .slaves = omap3xxx_gpio2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
- .class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
+static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 47, },
+ { .name = "rx", .dma_req = 48, },
+ { .dma_req = -1 }
};
-/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio3_dbck", },
+static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
+ { .role = "dbck", .clk = "omap_32k_fck", },
};
-static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
- &omap3xxx_l4_per__gpio3,
+/* See 35xx errata 2.1.1.128 in SPRZ278F */
+static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
+ .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
};
-static struct omap_hwmod omap3xxx_gpio3_hwmod = {
- .name = "gpio3",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio3_irqs,
- .main_clk = "gpio3_ick",
- .opt_clks = gpio3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
+ .name = "mmc2",
+ .mpu_irqs = omap34xx_mmc2_mpu_irqs,
+ .sdma_reqs = omap34xx_mmc2_sdma_reqs,
+ .opt_clks = omap34xx_mmc2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
+ .main_clk = "mmchs2_fck",
.prcm = {
.omap2 = {
+ .module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO3_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
+ .module_bit = OMAP3430_EN_MMC2_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
},
},
- .slaves = omap3xxx_gpio3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
- .class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
-
-/* gpio4 */
-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio4_dbck", },
-};
-
-static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
- &omap3xxx_l4_per__gpio4,
+ .dev_attr = &mmc2_pre_es3_dev_attr,
+ .class = &omap34xx_mmc_class,
};
-static struct omap_hwmod omap3xxx_gpio4_hwmod = {
- .name = "gpio4",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap2_gpio4_irqs,
- .main_clk = "gpio4_ick",
- .opt_clks = gpio4_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
+static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
+ .name = "mmc2",
+ .mpu_irqs = omap34xx_mmc2_mpu_irqs,
+ .sdma_reqs = omap34xx_mmc2_sdma_reqs,
+ .opt_clks = omap34xx_mmc2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
+ .main_clk = "mmchs2_fck",
.prcm = {
.omap2 = {
+ .module_offs = CORE_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO4_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
+ .module_bit = OMAP3430_EN_MMC2_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
},
},
- .slaves = omap3xxx_gpio4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
- .class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
+ .class = &omap34xx_mmc_class,
};
-/* gpio5 */
-static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
- { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
+/* MMC/SD/SDIO3 */
+
+static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
+ { .irq = 94, },
{ .irq = -1 }
};
-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio5_dbck", },
+static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 77, },
+ { .name = "rx", .dma_req = 78, },
+ { .dma_req = -1 }
};
-static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
- &omap3xxx_l4_per__gpio5,
+static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
+ { .role = "dbck", .clk = "omap_32k_fck", },
};
-static struct omap_hwmod omap3xxx_gpio5_hwmod = {
- .name = "gpio5",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap3xxx_gpio5_irqs,
- .main_clk = "gpio5_ick",
- .opt_clks = gpio5_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
+static struct omap_hwmod omap3xxx_mmc3_hwmod = {
+ .name = "mmc3",
+ .mpu_irqs = omap34xx_mmc3_mpu_irqs,
+ .sdma_reqs = omap34xx_mmc3_sdma_reqs,
+ .opt_clks = omap34xx_mmc3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
+ .main_clk = "mmchs3_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO5_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
+ .module_bit = OMAP3430_EN_MMC3_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
+ .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
},
},
- .slaves = omap3xxx_gpio5_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
- .class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
+ .class = &omap34xx_mmc_class,
};
-/* gpio6 */
-static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
- { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
- { .irq = -1 }
+/*
+ * 'usb_host_hs' class
+ * high-speed multi-port usb host controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio6_dbck", },
+static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
+ .name = "usb_host_hs",
+ .sysc = &omap3xxx_usb_host_hs_sysc,
};
-static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
- &omap3xxx_l4_per__gpio6,
+static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
+ { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
};
-static struct omap_hwmod omap3xxx_gpio6_hwmod = {
- .name = "gpio6",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap3xxx_gpio6_irqs,
- .main_clk = "gpio6_ick",
- .opt_clks = gpio6_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
- .prcm = {
+static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
+ { .name = "ohci-irq", .irq = 76 },
+ { .name = "ehci-irq", .irq = 77 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
+ .name = "usb_host_hs",
+ .class = &omap3xxx_usb_host_hs_hwmod_class,
+ .clkdm_name = "l3_init_clkdm",
+ .mpu_irqs = omap3xxx_usb_host_hs_irqs,
+ .main_clk = "usbhost_48m_fck",
+ .prcm = {
.omap2 = {
+ .module_offs = OMAP3430ES2_USBHOST_MOD,
.prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO6_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
+ .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
.idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
+ .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
+ .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
},
},
- .slaves = omap3xxx_gpio6_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
- .class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
-};
+ .opt_clks = omap3xxx_usb_host_hs_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
- .master = &omap3xxx_dma_system_hwmod,
- .slave = &omap3xxx_l3_main_hwmod,
- .clk = "core_l3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
+ /*
+ * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
+ * id: i660
+ *
+ * Description:
+ * In the following configuration :
+ * - USBHOST module is set to smart-idle mode
+ * - PRCM asserts idle_req to the USBHOST module ( This typically
+ * happens when the system is going to a low power mode : all ports
+ * have been suspended, the master part of the USBHOST module has
+ * entered the standby state, and SW has cut the functional clocks)
+ * - an USBHOST interrupt occurs before the module is able to answer
+ * idle_ack, typically a remote wakeup IRQ.
+ * Then the USB HOST module will enter a deadlock situation where it
+ * is no more accessible nor functional.
+ *
+ * Workaround:
+ * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
+ */
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
+ /*
+ * Errata: USB host EHCI may stall when entering smart-standby mode
+ * Id: i571
+ *
+ * Description:
+ * When the USBHOST module is set to smart-standby mode, and when it is
+ * ready to enter the standby state (i.e. all ports are suspended and
+ * all attached devices are in suspend mode), then it can wrongly assert
+ * the Mstandby signal too early while there are still some residual OCP
+ * transactions ongoing. If this condition occurs, the internal state
+ * machine may go to an undefined state and the USB link may be stuck
+ * upon the next resume.
+ *
+ * Workaround:
+ * Don't use smart standby; use only force standby,
+ * hence HWMOD_SWSUP_MSTANDBY
+ */
+
+ /*
+ * During system boot; If the hwmod framework resets the module
+ * the module will have smart idle settings; which can lead to deadlock
+ * (above Errata Id:i660); so, dont reset the module during boot;
+ * Use HWMOD_INIT_NO_RESET.
+ */
+
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ HWMOD_INIT_NO_RESET,
};
-static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
+/*
+ * 'usb_tll_hs' class
+ * usb_tll_hs module is the adapter on the usb_host_hs ports
+ */
+static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
.rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
-static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap3xxx_dma_sysc,
+static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
+ .name = "usb_tll_hs",
+ .sysc = &omap3xxx_usb_tll_hs_sysc,
};
-/* dma_system */
-static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
- {
- .pa_start = 0x48056000,
- .pa_end = 0x48056fff,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
+ { .name = "tll-irq", .irq = 78 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
+ .name = "usb_tll_hs",
+ .class = &omap3xxx_usb_tll_hs_hwmod_class,
+ .clkdm_name = "l3_init_clkdm",
+ .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
+ .main_clk = "usbtll_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 3,
+ .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
+ .idlest_reg_id = 3,
+ .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
+ },
},
- { }
};
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
- &omap3xxx_dma_system__l3,
+static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
+ .name = "hdq1w",
+ .mpu_irqs = omap2_hdq1w_mpu_irqs,
+ .main_clk = "hdq_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_HDQ_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
+ },
+ },
+ .class = &omap2_hdq1w_class,
};
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_dma_system_hwmod,
- .clk = "core_l4_ick",
- .addr = omap3xxx_dma_system_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/*
+ * '32K sync counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0004,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
- &omap3xxx_l4_core__dma_system,
+static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
+ .name = "counter",
+ .sysc = &omap3xxx_counter_sysc,
};
-static struct omap_hwmod omap3xxx_dma_system_hwmod = {
- .name = "dma",
- .class = &omap3xxx_dma_hwmod_class,
- .mpu_irqs = omap2_dma_system_irqs,
- .main_clk = "core_l3_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_ST_SDMA_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
+static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
+ .name = "counter_32k",
+ .class = &omap3xxx_counter_hwmod_class,
+ .clkdm_name = "wkup_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE,
+ .main_clk = "wkup_32k_fck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = WKUP_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
},
},
- .slaves = omap3xxx_dma_system_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
- .masters = omap3xxx_dma_system_masters,
- .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
- .dev_attr = &dma_dev_attr,
- .flags = HWMOD_NO_IDLEST,
};
/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
+ * interfaces
*/
-static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
- .sysc_offs = 0x008c,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
- .clockact = 0x2,
-};
-
-static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
- .name = "mcbsp",
- .sysc = &omap3xxx_mcbsp_sysc,
- .rev = MCBSP_CONFIG_TYPE3,
+/* L3 -> L4_CORE interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
+ .master = &omap3xxx_l3_main_hwmod,
+ .slave = &omap3xxx_l4_core_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp1 */
-static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
- { .name = "irq", .irq = 16 },
- { .name = "tx", .irq = 59 },
- { .name = "rx", .irq = 60 },
- { .irq = -1 }
+/* L3 -> L4_PER interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
+ .master = &omap3xxx_l3_main_hwmod,
+ .slave = &omap3xxx_l4_per_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
+static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
{
- .name = "mpu",
- .pa_start = 0x48074000,
- .pa_end = 0x480740ff,
- .flags = ADDR_TYPE_RT
+ .pa_start = 0x68000000,
+ .pa_end = 0x6800ffff,
+ .flags = ADDR_TYPE_RT,
},
{ }
};
-/* l4_core -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_mcbsp1_hwmod,
- .clk = "mcbsp1_ick",
- .addr = omap3xxx_mcbsp1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* MPU -> L3 interface */
+static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
+ .master = &omap3xxx_mpu_hwmod,
+ .slave = &omap3xxx_l3_main_hwmod,
+ .addr = omap3xxx_l3_main_addrs,
+ .user = OCP_USER_MPU,
};
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
- &omap3xxx_l4_core__mcbsp1,
+/* DSS -> l3 */
+static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
+ .master = &omap3430es1_dss_core_hwmod,
+ .slave = &omap3xxx_l3_main_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap3xxx_mcbsp_hwmod_class,
- .mpu_irqs = omap3xxx_mcbsp1_irqs,
- .sdma_reqs = omap2_mcbsp1_sdma_reqs,
- .main_clk = "mcbsp1_fck",
- .prcm = {
+static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
+ .master = &omap3xxx_dss_core_hwmod,
+ .slave = &omap3xxx_l3_main_hwmod,
+ .fw = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
- },
+ .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
+ .flags = OMAP_FIREWALL_L3,
+ }
},
- .slaves = omap3xxx_mcbsp1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp2 */
-static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
- { .name = "irq", .irq = 17 },
- { .name = "tx", .irq = 62 },
- { .name = "rx", .irq = 63 },
- { .irq = -1 }
+/* l3_core -> usbhsotg interface */
+static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
+ .master = &omap3xxx_usbhsotg_hwmod,
+ .slave = &omap3xxx_l3_main_hwmod,
+ .clk = "core_l3_ick",
+ .user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x49022000,
- .pa_end = 0x490220ff,
- .flags = ADDR_TYPE_RT
- },
- { }
+/* l3_core -> am35xx_usbhsotg interface */
+static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
+ .master = &am35xx_usbhsotg_hwmod,
+ .slave = &omap3xxx_l3_main_hwmod,
+ .clk = "core_l3_ick",
+ .user = OCP_USER_MPU,
};
-
-/* l4_per -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_mcbsp2_hwmod,
- .clk = "mcbsp2_ick",
- .addr = omap3xxx_mcbsp2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* L4_CORE -> L4_WKUP interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_l4_wkup_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
- &omap3xxx_l4_per__mcbsp2,
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_pre_es3_mmc1_hwmod,
+ .clk = "mmchs1_ick",
+ .addr = omap2430_mmc1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
};
-static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
- .sidetone = "mcbsp2_sidetone",
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_es3plus_mmc1_hwmod,
+ .clk = "mmchs1_ick",
+ .addr = omap2430_mmc1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
};
-static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap3xxx_mcbsp_hwmod_class,
- .mpu_irqs = omap3xxx_mcbsp2_irqs,
- .sdma_reqs = omap2_mcbsp2_sdma_reqs,
- .main_clk = "mcbsp2_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
- },
- },
- .slaves = omap3xxx_mcbsp2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
- .dev_attr = &omap34xx_mcbsp2_dev_attr,
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_pre_es3_mmc2_hwmod,
+ .clk = "mmchs2_ick",
+ .addr = omap2430_mmc2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
};
-/* mcbsp3 */
-static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
- { .name = "irq", .irq = 22 },
- { .name = "tx", .irq = 89 },
- { .name = "rx", .irq = 90 },
- { .irq = -1 }
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_es3plus_mmc2_hwmod,
+ .clk = "mmchs2_ick",
+ .addr = omap2430_mmc2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
};
-static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
+/* L4 CORE -> MMC3 interface */
+static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
{
- .name = "mpu",
- .pa_start = 0x49024000,
- .pa_end = 0x490240ff,
- .flags = ADDR_TYPE_RT
+ .pa_start = 0x480ad000,
+ .pa_end = 0x480ad1ff,
+ .flags = ADDR_TYPE_RT,
},
{ }
};
-/* l4_per -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_mcbsp3_hwmod,
- .clk = "mcbsp3_ick",
- .addr = omap3xxx_mcbsp3_addrs,
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_mmc3_hwmod,
+ .clk = "mmchs3_ick",
+ .addr = omap3xxx_mmc3_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
};
-/* mcbsp3 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
- &omap3xxx_l4_per__mcbsp3,
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
+ {
+ .pa_start = OMAP3_UART1_BASE,
+ .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
};
-static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
- .sidetone = "mcbsp3_sidetone",
+static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_uart1_hwmod,
+ .clk = "uart1_ick",
+ .addr = omap3xxx_uart1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
- .name = "mcbsp3",
- .class = &omap3xxx_mcbsp_hwmod_class,
- .mpu_irqs = omap3xxx_mcbsp3_irqs,
- .sdma_reqs = omap2_mcbsp3_sdma_reqs,
- .main_clk = "mcbsp3_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
- },
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
+ {
+ .pa_start = OMAP3_UART2_BASE,
+ .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
- .slaves = omap3xxx_mcbsp3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
- .dev_attr = &omap34xx_mcbsp3_dev_attr,
-};
-
-/* mcbsp4 */
-static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
- { .name = "irq", .irq = 23 },
- { .name = "tx", .irq = 54 },
- { .name = "rx", .irq = 55 },
- { .irq = -1 }
+ { }
};
-static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
- { .name = "rx", .dma_req = 20 },
- { .name = "tx", .dma_req = 19 },
- { .dma_req = -1 }
+static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_uart2_hwmod,
+ .clk = "uart2_ick",
+ .addr = omap3xxx_uart2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
{
- .name = "mpu",
- .pa_start = 0x49026000,
- .pa_end = 0x490260ff,
- .flags = ADDR_TYPE_RT
+ .pa_start = OMAP3_UART3_BASE,
+ .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
-/* l4_per -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
+static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
.master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_mcbsp4_hwmod,
- .clk = "mcbsp4_ick",
- .addr = omap3xxx_mcbsp4_addrs,
+ .slave = &omap3xxx_uart3_hwmod,
+ .clk = "uart3_ick",
+ .addr = omap3xxx_uart3_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp4 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
- &omap3xxx_l4_per__mcbsp4,
-};
-
-static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
- .name = "mcbsp4",
- .class = &omap3xxx_mcbsp_hwmod_class,
- .mpu_irqs = omap3xxx_mcbsp4_irqs,
- .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
- .main_clk = "mcbsp4_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
- },
+/* L4 PER -> UART4 interface */
+static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
+ {
+ .pa_start = OMAP3_UART4_BASE,
+ .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
- .slaves = omap3xxx_mcbsp4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
-};
-
-/* mcbsp5 */
-static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
- { .name = "irq", .irq = 27 },
- { .name = "tx", .irq = 81 },
- { .name = "rx", .irq = 82 },
- { .irq = -1 }
+ { }
};
-static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
- { .name = "rx", .dma_req = 22 },
- { .name = "tx", .dma_req = 21 },
- { .dma_req = -1 }
+static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap36xx_uart4_hwmod,
+ .clk = "uart4_ick",
+ .addr = omap36xx_uart4_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
+/* AM35xx: L4 CORE -> UART4 interface */
+static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
{
- .name = "mpu",
- .pa_start = 0x48096000,
- .pa_end = 0x480960ff,
- .flags = ADDR_TYPE_RT
+ .pa_start = OMAP3_UART4_AM35XX_BASE,
+ .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
- { }
};
-/* l4_core -> mcbsp5 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
+static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
.master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_mcbsp5_hwmod,
- .clk = "mcbsp5_ick",
- .addr = omap3xxx_mcbsp5_addrs,
+ .slave = &am35xx_uart4_hwmod,
+ .clk = "uart4_ick",
+ .addr = am35xx_uart4_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp5 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
- &omap3xxx_l4_core__mcbsp5,
-};
-
-static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
- .name = "mcbsp5",
- .class = &omap3xxx_mcbsp_hwmod_class,
- .mpu_irqs = omap3xxx_mcbsp5_irqs,
- .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
- .main_clk = "mcbsp5_fck",
- .prcm = {
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_i2c1_hwmod,
+ .clk = "i2c1_ick",
+ .addr = omap2_i2c1_addr_space,
+ .fw = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
- },
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
+ .l4_prot_group = 7,
+ .flags = OMAP_FIREWALL_L4,
+ }
},
- .slaves = omap3xxx_mcbsp5_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
-};
-/* 'mcbsp sidetone' class */
-
-static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
- .sysc_offs = 0x0010,
- .sysc_flags = SYSC_HAS_AUTOIDLE,
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
- .name = "mcbsp_sidetone",
- .sysc = &omap3xxx_mcbsp_sidetone_sysc,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcbsp2_sidetone */
-static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
- { .name = "irq", .irq = 4 },
- { .irq = -1 }
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_i2c2_hwmod,
+ .clk = "i2c2_ick",
+ .addr = omap2_i2c2_addr_space,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
+ .l4_prot_group = 7,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
+/* L4 CORE -> I2C3 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
{
- .name = "sidetone",
- .pa_start = 0x49028000,
- .pa_end = 0x490280ff,
- .flags = ADDR_TYPE_RT
+ .pa_start = 0x48060000,
+ .pa_end = 0x48060000 + SZ_128 - 1,
+ .flags = ADDR_TYPE_RT,
},
{ }
};
-/* l4_per -> mcbsp2_sidetone */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
- .clk = "mcbsp2_ick",
- .addr = omap3xxx_mcbsp2_sidetone_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* mcbsp2_sidetone slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
- &omap3xxx_l4_per__mcbsp2_sidetone,
-};
-
-static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
- .name = "mcbsp2_sidetone",
- .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
- .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
- .main_clk = "mcbsp2_fck",
- .prcm = {
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_i2c3_hwmod,
+ .clk = "i2c3_ick",
+ .addr = omap3xxx_i2c3_addr_space,
+ .fw = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
- },
- },
- .slaves = omap3xxx_mcbsp2_sidetone_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
-};
-
-/* mcbsp3_sidetone */
-static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
- { .name = "irq", .irq = 5 },
- { .irq = -1 }
+ .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
+ .l4_prot_group = 7,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
{
- .name = "sidetone",
- .pa_start = 0x4902A000,
- .pa_end = 0x4902A0ff,
- .flags = ADDR_TYPE_RT
+ .pa_start = OMAP34XX_SR1_BASE,
+ .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
},
{ }
};
-/* l4_per -> mcbsp3_sidetone */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
- .clk = "mcbsp3_ick",
- .addr = omap3xxx_mcbsp3_sidetone_addrs,
+static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap34xx_sr1_hwmod,
+ .clk = "sr_l4_ick",
+ .addr = omap3_sr1_addr_space,
.user = OCP_USER_MPU,
};
-/* mcbsp3_sidetone slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
- &omap3xxx_l4_per__mcbsp3_sidetone,
+static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap36xx_sr1_hwmod,
+ .clk = "sr_l4_ick",
+ .addr = omap3_sr1_addr_space,
+ .user = OCP_USER_MPU,
};
-static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
- .name = "mcbsp3_sidetone",
- .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
- .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
- .main_clk = "mcbsp3_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
- },
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
+ {
+ .pa_start = OMAP34XX_SR2_BASE,
+ .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
},
- .slaves = omap3xxx_mcbsp3_sidetone_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
-};
-
-
-/* SR common */
-static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
- .clkact_shift = 20,
+ { }
};
-static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
- .sysc_offs = 0x24,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
- .clockact = CLOCKACT_TEST_ICLK,
- .sysc_fields = &omap34xx_sr_sysc_fields,
+static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap34xx_sr2_hwmod,
+ .clk = "sr_l4_ick",
+ .addr = omap3_sr2_addr_space,
+ .user = OCP_USER_MPU,
};
-static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
- .name = "smartreflex",
- .sysc = &omap34xx_sr_sysc,
- .rev = 1,
+static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap36xx_sr2_hwmod,
+ .clk = "sr_l4_ick",
+ .addr = omap3_sr2_addr_space,
+ .user = OCP_USER_MPU,
};
-static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
- .sidle_shift = 24,
- .enwkup_shift = 26
+static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
+ {
+ .pa_start = OMAP34XX_HSUSB_OTG_BASE,
+ .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
- .sysc_offs = 0x38,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
- SYSC_NO_CACHE),
- .sysc_fields = &omap36xx_sr_sysc_fields,
+/* l4_core -> usbhsotg */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_usbhsotg_hwmod,
+ .clk = "l4_ick",
+ .addr = omap3xxx_usbhsotg_addrs,
+ .user = OCP_USER_MPU,
};
-static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
- .name = "smartreflex",
- .sysc = &omap36xx_sr_sysc,
- .rev = 2,
+static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
+ {
+ .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
+ .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-/* SR1 */
-static struct omap_smartreflex_dev_attr sr1_dev_attr = {
- .sensor_voltdm_name = "mpu_iva",
+/* l4_core -> usbhsotg */
+static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &am35xx_usbhsotg_hwmod,
+ .clk = "l4_ick",
+ .addr = am35xx_usbhsotg_addrs,
+ .user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
- &omap3_l4_core__sr1,
+/* L4_WKUP -> L4_SEC interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
+ .master = &omap3xxx_l4_wkup_hwmod,
+ .slave = &omap3xxx_l4_sec_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap34xx_sr1_hwmod = {
- .name = "sr1_hwmod",
- .class = &omap34xx_smartreflex_hwmod_class,
- .main_clk = "sr1_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SR1_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
- },
- },
- .slaves = omap3_sr1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
- .dev_attr = &sr1_dev_attr,
- .mpu_irqs = omap3_smartreflex_mpu_irqs,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
+/* IVA2 <- L3 interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
+ .master = &omap3xxx_l3_main_hwmod,
+ .slave = &omap3xxx_iva_hwmod,
+ .clk = "core_l3_ick",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap36xx_sr1_hwmod = {
- .name = "sr1_hwmod",
- .class = &omap36xx_smartreflex_hwmod_class,
- .main_clk = "sr1_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SR1_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
- },
+static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+ {
+ .pa_start = 0x48318000,
+ .pa_end = 0x48318000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap3_sr1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
- .dev_attr = &sr1_dev_attr,
- .mpu_irqs = omap3_smartreflex_mpu_irqs,
+ { }
};
-/* SR2 */
-static struct omap_smartreflex_dev_attr sr2_dev_attr = {
- .sensor_voltdm_name = "core",
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
+ .master = &omap3xxx_l4_wkup_hwmod,
+ .slave = &omap3xxx_timer1_hwmod,
+ .clk = "gpt1_ick",
+ .addr = omap3xxx_timer1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
- &omap3_l4_core__sr2,
+static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+ {
+ .pa_start = 0x49032000,
+ .pa_end = 0x49032000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod omap34xx_sr2_hwmod = {
- .name = "sr2_hwmod",
- .class = &omap34xx_smartreflex_hwmod_class,
- .main_clk = "sr2_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SR2_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
- },
- },
- .slaves = omap3_sr2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
- .dev_attr = &sr2_dev_attr,
- .mpu_irqs = omap3_smartreflex_core_irqs,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer2_hwmod,
+ .clk = "gpt2_ick",
+ .addr = omap3xxx_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap36xx_sr2_hwmod = {
- .name = "sr2_hwmod",
- .class = &omap36xx_smartreflex_hwmod_class,
- .main_clk = "sr2_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SR2_SHIFT,
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
- },
+static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
+ {
+ .pa_start = 0x49034000,
+ .pa_end = 0x49034000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap3_sr2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
- .dev_attr = &sr2_dev_attr,
- .mpu_irqs = omap3_smartreflex_core_irqs,
+ { }
};
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors
- * using a queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
- .rev_offs = 0x000,
- .sysc_offs = 0x010,
- .syss_offs = 0x014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer3_hwmod,
+ .clk = "gpt3_ick",
+ .addr = omap3xxx_timer3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &omap3xxx_mailbox_sysc,
+static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
+ {
+ .pa_start = 0x49036000,
+ .pa_end = 0x49036000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod omap3xxx_mailbox_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
- { .irq = 26 },
- { .irq = -1 }
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer4_hwmod,
+ .clk = "gpt4_ick",
+ .addr = omap3xxx_timer4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
{
- .pa_start = 0x48094000,
- .pa_end = 0x480941ff,
- .flags = ADDR_TYPE_RT,
+ .pa_start = 0x49038000,
+ .pa_end = 0x49038000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
},
{ }
};
-/* l4_core -> mailbox */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_mailbox_hwmod,
- .addr = omap3xxx_mailbox_addrs,
+/* l4_per -> timer5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer5_hwmod,
+ .clk = "gpt5_ick",
+ .addr = omap3xxx_timer5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
- &omap3xxx_l4_core__mailbox,
-};
-
-static struct omap_hwmod omap3xxx_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap3xxx_mailbox_hwmod_class,
- .mpu_irqs = omap3xxx_mailbox_irqs,
- .main_clk = "mailboxes_ick",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
- },
+static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
+ {
+ .pa_start = 0x4903A000,
+ .pa_end = 0x4903A000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap3xxx_mailbox_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
+ { }
};
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap34xx_mcspi1,
- .clk = "mcspi1_ick",
- .addr = omap2_mcspi1_addr_space,
+/* l4_per -> timer6 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer6_hwmod,
+ .clk = "gpt6_ick",
+ .addr = omap3xxx_timer6_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap34xx_mcspi2,
- .clk = "mcspi2_ick",
- .addr = omap2_mcspi2_addr_space,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
+ {
+ .pa_start = 0x4903C000,
+ .pa_end = 0x4903C000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-/* l4 core -> mcspi3 interface */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap34xx_mcspi3,
- .clk = "mcspi3_ick",
- .addr = omap2430_mcspi3_addr_space,
+/* l4_per -> timer7 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer7_hwmod,
+ .clk = "gpt7_ick",
+ .addr = omap3xxx_timer7_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4 core -> mcspi4 interface */
-static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
+static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
{
- .pa_start = 0x480ba000,
- .pa_end = 0x480ba0ff,
- .flags = ADDR_TYPE_RT,
+ .pa_start = 0x4903E000,
+ .pa_end = 0x4903E000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
},
{ }
};
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap34xx_mcspi4,
- .clk = "mcspi4_ick",
- .addr = omap34xx_mcspi4_addr_space,
+/* l4_per -> timer8 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer8_hwmod,
+ .clk = "gpt8_ick",
+ .addr = omap3xxx_timer8_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/*
- * 'mcspi' class
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
- * bus
- */
-
-static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
+static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
+ {
+ .pa_start = 0x49040000,
+ .pa_end = 0x49040000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod_class omap34xx_mcspi_class = {
- .name = "mcspi",
- .sysc = &omap34xx_mcspi_sysc,
- .rev = OMAP3_MCSPI_REV,
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_timer9_hwmod,
+ .clk = "gpt9_ick",
+ .addr = omap3xxx_timer9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcspi1 */
-static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
- &omap34xx_l4_core__mcspi1,
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_timer10_hwmod,
+ .clk = "gpt10_ick",
+ .addr = omap2_timer10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
- .num_chipselect = 4,
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_timer11_hwmod,
+ .clk = "gpt11_ick",
+ .addr = omap2_timer11_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap34xx_mcspi1 = {
- .name = "mcspi1",
- .mpu_irqs = omap2_mcspi1_mpu_irqs,
- .sdma_reqs = omap2_mcspi1_sdma_reqs,
- .main_clk = "mcspi1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
- },
+static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
+ {
+ .pa_start = 0x48304000,
+ .pa_end = 0x48304000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap34xx_mcspi1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
- .class = &omap34xx_mcspi_class,
- .dev_attr = &omap_mcspi1_dev_attr,
+ { }
};
-/* mcspi2 */
-static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
- &omap34xx_l4_core__mcspi2,
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
+ .master = &omap3xxx_l4_sec_hwmod,
+ .slave = &omap3xxx_timer12_hwmod,
+ .clk = "gpt12_ick",
+ .addr = omap3xxx_timer12_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
- .num_chipselect = 2,
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
+ {
+ .pa_start = 0x48314000,
+ .pa_end = 0x4831407f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod omap34xx_mcspi2 = {
- .name = "mcspi2",
- .mpu_irqs = omap2_mcspi2_mpu_irqs,
- .sdma_reqs = omap2_mcspi2_sdma_reqs,
- .main_clk = "mcspi2_fck",
- .prcm = {
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
+ .master = &omap3xxx_l4_wkup_hwmod,
+ .slave = &omap3xxx_wd_timer2_hwmod,
+ .clk = "wdt2_ick",
+ .addr = omap3xxx_wd_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss */
+static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3430es1_dss_core_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2_dss_addrs,
+ .fw = {
.omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
- },
+ .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+ .flags = OMAP_FIREWALL_L4,
+ }
},
- .slaves = omap34xx_mcspi2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
- .class = &omap34xx_mcspi_class,
- .dev_attr = &omap_mcspi2_dev_attr,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* mcspi3 */
-static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
- { .name = "irq", .irq = 91 }, /* 91 */
- { .irq = -1 }
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dss_core_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2_dss_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 15 },
- { .name = "rx0", .dma_req = 16 },
- { .name = "tx1", .dma_req = 23 },
- { .name = "rx1", .dma_req = 24 },
- { .dma_req = -1 }
+/* l4_core -> dss_dispc */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dss_dispc_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2_dss_dispc_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
- &omap34xx_l4_core__mcspi3,
+static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
+ {
+ .pa_start = 0x4804FC00,
+ .pa_end = 0x4804FFFF,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
- .num_chipselect = 2,
+/* l4_core -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dss_dsi1_hwmod,
+ .clk = "dss_ick",
+ .addr = omap3xxx_dss_dsi1_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap34xx_mcspi3 = {
- .name = "mcspi3",
- .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
- .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
- .main_clk = "mcspi3_fck",
- .prcm = {
+/* l4_core -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dss_rfbi_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2_dss_rfbi_addrs,
+ .fw = {
.omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
- },
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
+ .flags = OMAP_FIREWALL_L4,
+ }
},
- .slaves = omap34xx_mcspi3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
- .class = &omap34xx_mcspi_class,
- .dev_attr = &omap_mcspi3_dev_attr,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* SPI4 */
-static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
- { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
- { .irq = -1 }
+/* l4_core -> dss_venc */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dss_venc_hwmod,
+ .clk = "dss_ick",
+ .addr = omap2_dss_venc_addrs,
+ .fw = {
+ .omap2 = {
+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
+ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
- { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
- { .dma_req = -1 }
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
+ {
+ .pa_start = 0x48310000,
+ .pa_end = 0x483101ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
- &omap34xx_l4_core__mcspi4,
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
+ .master = &omap3xxx_l4_wkup_hwmod,
+ .slave = &omap3xxx_gpio1_hwmod,
+ .addr = omap3xxx_gpio1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
- .num_chipselect = 1,
+/* l4_per -> gpio2 */
+static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
+ {
+ .pa_start = 0x49050000,
+ .pa_end = 0x490501ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod omap34xx_mcspi4 = {
- .name = "mcspi4",
- .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
- .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
- .main_clk = "mcspi4_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
- },
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio2_hwmod,
+ .addr = omap3xxx_gpio2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
+ {
+ .pa_start = 0x49052000,
+ .pa_end = 0x490521ff,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap34xx_mcspi4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
- .class = &omap34xx_mcspi_class,
- .dev_attr = &omap_mcspi4_dev_attr,
+ { }
};
-/*
- * usbhsotg
- */
-static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
- .rev_offs = 0x0400,
- .sysc_offs = 0x0404,
- .syss_offs = 0x0408,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio3_hwmod,
+ .addr = omap3xxx_gpio3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_class usbotg_class = {
- .name = "usbotg",
- .sysc = &omap3xxx_usbhsotg_sysc,
+/* l4_per -> gpio4 */
+static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
+ {
+ .pa_start = 0x49054000,
+ .pa_end = 0x490541ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-/* usb_otg_hs */
-static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
- { .name = "mc", .irq = 92 },
- { .name = "dma", .irq = 93 },
- { .irq = -1 }
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio4_hwmod,
+ .addr = omap3xxx_gpio4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
- .name = "usb_otg_hs",
- .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
- .main_clk = "hsotgusb_ick",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
- .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
- },
+/* l4_per -> gpio5 */
+static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
+ {
+ .pa_start = 0x49056000,
+ .pa_end = 0x490561ff,
+ .flags = ADDR_TYPE_RT
},
- .masters = omap3xxx_usbhsotg_masters,
- .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
- .slaves = omap3xxx_usbhsotg_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
- .class = &usbotg_class,
+ { }
+};
- /*
- * Erratum ID: i479 idle_req / idle_ack mechanism potentially
- * broken when autoidle is enabled
- * workaround is to disable the autoidle bit at module level.
- */
- .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
- | HWMOD_SWSUP_MSTANDBY,
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio5_hwmod,
+ .addr = omap3xxx_gpio5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* usb_otg_hs */
-static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
+/* l4_per -> gpio6 */
+static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
+ {
+ .pa_start = 0x49058000,
+ .pa_end = 0x490581ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
- { .name = "mc", .irq = 71 },
- { .irq = -1 }
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_gpio6_hwmod,
+ .addr = omap3xxx_gpio6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_class am35xx_usbotg_class = {
- .name = "am35xx_usbotg",
- .sysc = NULL,
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
+ .master = &omap3xxx_dma_system_hwmod,
+ .slave = &omap3xxx_l3_main_hwmod,
+ .clk = "core_l3_ick",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod am35xx_usbhsotg_hwmod = {
- .name = "am35x_otg_hs",
- .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
- .main_clk = NULL,
- .prcm = {
- .omap2 = {
- },
+static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
+ {
+ .pa_start = 0x48056000,
+ .pa_end = 0x48056fff,
+ .flags = ADDR_TYPE_RT
},
- .masters = am35xx_usbhsotg_masters,
- .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
- .slaves = am35xx_usbhsotg_slaves,
- .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
- .class = &am35xx_usbotg_class,
+ { }
};
-/* MMC/SD/SDIO common */
-
-static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
- .rev_offs = 0x1fc,
- .sysc_offs = 0x10,
- .syss_offs = 0x14,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_dma_system_hwmod,
+ .clk = "core_l4_ick",
+ .addr = omap3xxx_dma_system_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_class omap34xx_mmc_class = {
- .name = "mmc",
- .sysc = &omap34xx_mmc_sysc,
+static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x48074000,
+ .pa_end = 0x480740ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-/* MMC/SD/SDIO1 */
-
-static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
- { .irq = 83, },
- { .irq = -1 }
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_mcbsp1_hwmod,
+ .clk = "mcbsp1_ick",
+ .addr = omap3xxx_mcbsp1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
- { .name = "tx", .dma_req = 61, },
- { .name = "rx", .dma_req = 62, },
- { .dma_req = -1 }
+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x49022000,
+ .pa_end = 0x490220ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
- { .role = "dbck", .clk = "omap_32k_fck", },
+/* l4_per -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_mcbsp2_hwmod,
+ .clk = "mcbsp2_ick",
+ .addr = omap3xxx_mcbsp2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
- &omap3xxx_l4_core__mmc1,
+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x49024000,
+ .pa_end = 0x490240ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_mmc_dev_attr mmc1_dev_attr = {
- .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+/* l4_per -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_mcbsp3_hwmod,
+ .clk = "mcbsp3_ick",
+ .addr = omap3xxx_mcbsp3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* See 35xx errata 2.1.1.128 in SPRZ278F */
-static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
- .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
- OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
+static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x49026000,
+ .pa_end = 0x490260ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
- .name = "mmc1",
- .mpu_irqs = omap34xx_mmc1_mpu_irqs,
- .sdma_reqs = omap34xx_mmc1_sdma_reqs,
- .opt_clks = omap34xx_mmc1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
- .main_clk = "mmchs1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MMC1_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
- },
- },
- .dev_attr = &mmc1_pre_es3_dev_attr,
- .slaves = omap3xxx_mmc1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
- .class = &omap34xx_mmc_class,
+/* l4_per -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_mcbsp4_hwmod,
+ .clk = "mcbsp4_ick",
+ .addr = omap3xxx_mcbsp4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
- .name = "mmc1",
- .mpu_irqs = omap34xx_mmc1_mpu_irqs,
- .sdma_reqs = omap34xx_mmc1_sdma_reqs,
- .opt_clks = omap34xx_mmc1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
- .main_clk = "mmchs1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MMC1_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
- },
+static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x48096000,
+ .pa_end = 0x480960ff,
+ .flags = ADDR_TYPE_RT
},
- .dev_attr = &mmc1_dev_attr,
- .slaves = omap3xxx_mmc1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
- .class = &omap34xx_mmc_class,
+ { }
};
-/* MMC/SD/SDIO2 */
-
-static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
- { .irq = INT_24XX_MMC2_IRQ, },
- { .irq = -1 }
+/* l4_core -> mcbsp5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_mcbsp5_hwmod,
+ .clk = "mcbsp5_ick",
+ .addr = omap3xxx_mcbsp5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
- { .name = "tx", .dma_req = 47, },
- { .name = "rx", .dma_req = 48, },
- { .dma_req = -1 }
+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
+ {
+ .name = "sidetone",
+ .pa_start = 0x49028000,
+ .pa_end = 0x490280ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
- { .role = "dbck", .clk = "omap_32k_fck", },
+/* l4_per -> mcbsp2_sidetone */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
+ .clk = "mcbsp2_ick",
+ .addr = omap3xxx_mcbsp2_sidetone_addrs,
+ .user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
- &omap3xxx_l4_core__mmc2,
+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
+ {
+ .name = "sidetone",
+ .pa_start = 0x4902A000,
+ .pa_end = 0x4902A0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-/* See 35xx errata 2.1.1.128 in SPRZ278F */
-static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
- .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
+/* l4_per -> mcbsp3_sidetone */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
+ .master = &omap3xxx_l4_per_hwmod,
+ .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
+ .clk = "mcbsp3_ick",
+ .addr = omap3xxx_mcbsp3_sidetone_addrs,
+ .user = OCP_USER_MPU,
};
-static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
- .name = "mmc2",
- .mpu_irqs = omap34xx_mmc2_mpu_irqs,
- .sdma_reqs = omap34xx_mmc2_sdma_reqs,
- .opt_clks = omap34xx_mmc2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
- .main_clk = "mmchs2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MMC2_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
- },
+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
},
- .dev_attr = &mmc2_pre_es3_dev_attr,
- .slaves = omap3xxx_mmc2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
- .class = &omap34xx_mmc_class,
+ { }
};
-static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
- .name = "mmc2",
- .mpu_irqs = omap34xx_mmc2_mpu_irqs,
- .sdma_reqs = omap34xx_mmc2_sdma_reqs,
- .opt_clks = omap34xx_mmc2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
- .main_clk = "mmchs2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MMC2_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
- },
- },
- .slaves = omap3xxx_mmc2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
- .class = &omap34xx_mmc_class,
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_mailbox_hwmod,
+ .addr = omap3xxx_mailbox_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* MMC/SD/SDIO3 */
-
-static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
- { .irq = 94, },
- { .irq = -1 }
+/* l4 core -> mcspi1 interface */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap34xx_mcspi1,
+ .clk = "mcspi1_ick",
+ .addr = omap2_mcspi1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
- { .name = "tx", .dma_req = 77, },
- { .name = "rx", .dma_req = 78, },
- { .dma_req = -1 }
+/* l4 core -> mcspi2 interface */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap34xx_mcspi2,
+ .clk = "mcspi2_ick",
+ .addr = omap2_mcspi2_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
- { .role = "dbck", .clk = "omap_32k_fck", },
+/* l4 core -> mcspi3 interface */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap34xx_mcspi3,
+ .clk = "mcspi3_ick",
+ .addr = omap2430_mcspi3_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
- &omap3xxx_l4_core__mmc3,
+/* l4 core -> mcspi4 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
+ {
+ .pa_start = 0x480ba000,
+ .pa_end = 0x480ba0ff,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
};
-static struct omap_hwmod omap3xxx_mmc3_hwmod = {
- .name = "mmc3",
- .mpu_irqs = omap34xx_mmc3_mpu_irqs,
- .sdma_reqs = omap34xx_mmc3_sdma_reqs,
- .opt_clks = omap34xx_mmc3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
- .main_clk = "mmchs3_fck",
- .prcm = {
- .omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MMC3_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
- },
- },
- .slaves = omap3xxx_mmc3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
- .class = &omap34xx_mmc_class,
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap34xx_mcspi4,
+ .clk = "mcspi4_ick",
+ .addr = omap34xx_mcspi4_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/*
- * 'usb_host_hs' class
- * high-speed multi-port usb host controller
- */
static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
.master = &omap3xxx_usb_host_hs_hwmod,
.slave = &omap3xxx_l3_main_hwmod,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
- .name = "usb_host_hs",
- .sysc = &omap3xxx_usb_host_hs_sysc,
-};
-
-static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
- &omap3xxx_usb_host_hs__l3_main_2,
-};
-
static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
{
.name = "uhh",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
- &omap3xxx_l4_core__usb_host_hs,
-};
-
-static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
- { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
-};
-
-static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
- { .name = "ohci-irq", .irq = 76 },
- { .name = "ehci-irq", .irq = 77 },
- { .irq = -1 }
-};
-
-static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
- .name = "usb_host_hs",
- .class = &omap3xxx_usb_host_hs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .mpu_irqs = omap3xxx_usb_host_hs_irqs,
- .main_clk = "usbhost_48m_fck",
- .prcm = {
- .omap2 = {
- .module_offs = OMAP3430ES2_USBHOST_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
- .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
- },
- },
- .opt_clks = omap3xxx_usb_host_hs_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
- .slaves = omap3xxx_usb_host_hs_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
- .masters = omap3xxx_usb_host_hs_masters,
- .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
-
- /*
- * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
- * id: i660
- *
- * Description:
- * In the following configuration :
- * - USBHOST module is set to smart-idle mode
- * - PRCM asserts idle_req to the USBHOST module ( This typically
- * happens when the system is going to a low power mode : all ports
- * have been suspended, the master part of the USBHOST module has
- * entered the standby state, and SW has cut the functional clocks)
- * - an USBHOST interrupt occurs before the module is able to answer
- * idle_ack, typically a remote wakeup IRQ.
- * Then the USB HOST module will enter a deadlock situation where it
- * is no more accessible nor functional.
- *
- * Workaround:
- * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
- */
-
- /*
- * Errata: USB host EHCI may stall when entering smart-standby mode
- * Id: i571
- *
- * Description:
- * When the USBHOST module is set to smart-standby mode, and when it is
- * ready to enter the standby state (i.e. all ports are suspended and
- * all attached devices are in suspend mode), then it can wrongly assert
- * the Mstandby signal too early while there are still some residual OCP
- * transactions ongoing. If this condition occurs, the internal state
- * machine may go to an undefined state and the USB link may be stuck
- * upon the next resume.
- *
- * Workaround:
- * Don't use smart standby; use only force standby,
- * hence HWMOD_SWSUP_MSTANDBY
- */
-
- /*
- * During system boot; If the hwmod framework resets the module
- * the module will have smart idle settings; which can lead to deadlock
- * (above Errata Id:i660); so, dont reset the module during boot;
- * Use HWMOD_INIT_NO_RESET.
- */
-
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
- HWMOD_INIT_NO_RESET,
-};
-
-/*
- * 'usb_tll_hs' class
- * usb_tll_hs module is the adapter on the usb_host_hs ports
- */
-static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
- .name = "usb_tll_hs",
- .sysc = &omap3xxx_usb_tll_hs_sysc,
-};
-
-static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
- { .name = "tll-irq", .irq = 78 },
- { .irq = -1 }
-};
-
static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
{
.name = "tll",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
- &omap3xxx_l4_core__usb_tll_hs,
+/* l4_core -> hdq1w interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_hdq1w_hwmod,
+ .clk = "hdq_ick",
+ .addr = omap2_hdq1w_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
-static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
- .name = "usb_tll_hs",
- .class = &omap3xxx_usb_tll_hs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
- .main_clk = "usbtll_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .prcm_reg_id = 3,
- .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
- .idlest_reg_id = 3,
- .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
- },
+/* l4_wkup -> 32ksync_counter */
+static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
+ {
+ .pa_start = 0x48320000,
+ .pa_end = 0x4832001f,
+ .flags = ADDR_TYPE_RT
},
- .slaves = omap3xxx_usb_tll_hs_slaves,
- .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
-};
-
-static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
- &omap3xxx_l3_main_hwmod,
- &omap3xxx_l4_core_hwmod,
- &omap3xxx_l4_per_hwmod,
- &omap3xxx_l4_wkup_hwmod,
- &omap3xxx_mmc3_hwmod,
- &omap3xxx_mpu_hwmod,
-
- &omap3xxx_timer1_hwmod,
- &omap3xxx_timer2_hwmod,
- &omap3xxx_timer3_hwmod,
- &omap3xxx_timer4_hwmod,
- &omap3xxx_timer5_hwmod,
- &omap3xxx_timer6_hwmod,
- &omap3xxx_timer7_hwmod,
- &omap3xxx_timer8_hwmod,
- &omap3xxx_timer9_hwmod,
- &omap3xxx_timer10_hwmod,
- &omap3xxx_timer11_hwmod,
-
- &omap3xxx_wd_timer2_hwmod,
- &omap3xxx_uart1_hwmod,
- &omap3xxx_uart2_hwmod,
- &omap3xxx_uart3_hwmod,
-
- /* i2c class */
- &omap3xxx_i2c1_hwmod,
- &omap3xxx_i2c2_hwmod,
- &omap3xxx_i2c3_hwmod,
-
- /* gpio class */
- &omap3xxx_gpio1_hwmod,
- &omap3xxx_gpio2_hwmod,
- &omap3xxx_gpio3_hwmod,
- &omap3xxx_gpio4_hwmod,
- &omap3xxx_gpio5_hwmod,
- &omap3xxx_gpio6_hwmod,
-
- /* dma_system class*/
- &omap3xxx_dma_system_hwmod,
-
- /* mcbsp class */
- &omap3xxx_mcbsp1_hwmod,
- &omap3xxx_mcbsp2_hwmod,
- &omap3xxx_mcbsp3_hwmod,
- &omap3xxx_mcbsp4_hwmod,
- &omap3xxx_mcbsp5_hwmod,
- &omap3xxx_mcbsp2_sidetone_hwmod,
- &omap3xxx_mcbsp3_sidetone_hwmod,
-
-
- /* mcspi class */
- &omap34xx_mcspi1,
- &omap34xx_mcspi2,
- &omap34xx_mcspi3,
- &omap34xx_mcspi4,
+ { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
+ .master = &omap3xxx_l4_wkup_hwmod,
+ .slave = &omap3xxx_counter_32k_hwmod,
+ .clk = "omap_32ksync_ick",
+ .addr = omap3xxx_counter_32k_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_l3_main__l4_core,
+ &omap3xxx_l3_main__l4_per,
+ &omap3xxx_mpu__l3_main,
+ &omap3xxx_l4_core__l4_wkup,
+ &omap3xxx_l4_core__mmc3,
+ &omap3_l4_core__uart1,
+ &omap3_l4_core__uart2,
+ &omap3_l4_per__uart3,
+ &omap3_l4_core__i2c1,
+ &omap3_l4_core__i2c2,
+ &omap3_l4_core__i2c3,
+ &omap3xxx_l4_wkup__l4_sec,
+ &omap3xxx_l4_wkup__timer1,
+ &omap3xxx_l4_per__timer2,
+ &omap3xxx_l4_per__timer3,
+ &omap3xxx_l4_per__timer4,
+ &omap3xxx_l4_per__timer5,
+ &omap3xxx_l4_per__timer6,
+ &omap3xxx_l4_per__timer7,
+ &omap3xxx_l4_per__timer8,
+ &omap3xxx_l4_per__timer9,
+ &omap3xxx_l4_core__timer10,
+ &omap3xxx_l4_core__timer11,
+ &omap3xxx_l4_wkup__wd_timer2,
+ &omap3xxx_l4_wkup__gpio1,
+ &omap3xxx_l4_per__gpio2,
+ &omap3xxx_l4_per__gpio3,
+ &omap3xxx_l4_per__gpio4,
+ &omap3xxx_l4_per__gpio5,
+ &omap3xxx_l4_per__gpio6,
+ &omap3xxx_dma_system__l3,
+ &omap3xxx_l4_core__dma_system,
+ &omap3xxx_l4_core__mcbsp1,
+ &omap3xxx_l4_per__mcbsp2,
+ &omap3xxx_l4_per__mcbsp3,
+ &omap3xxx_l4_per__mcbsp4,
+ &omap3xxx_l4_core__mcbsp5,
+ &omap3xxx_l4_per__mcbsp2_sidetone,
+ &omap3xxx_l4_per__mcbsp3_sidetone,
+ &omap34xx_l4_core__mcspi1,
+ &omap34xx_l4_core__mcspi2,
+ &omap34xx_l4_core__mcspi3,
+ &omap34xx_l4_core__mcspi4,
+ &omap3xxx_l4_wkup__counter_32k,
NULL,
};
-/* GP-only hwmods */
-static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
- &omap3xxx_timer12_hwmod,
+/* GP-only hwmod links */
+static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_l4_sec__timer12,
NULL
};
-/* 3430ES1-only hwmods */
-static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
- &omap3430es1_dss_core_hwmod,
+/* 3430ES1-only hwmod links */
+static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
+ &omap3430es1_dss__l3,
+ &omap3430es1_l4_core__dss,
NULL
};
-/* 3430ES2+-only hwmods */
-static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
- &omap3xxx_dss_core_hwmod,
- &omap3xxx_usbhsotg_hwmod,
- &omap3xxx_usb_host_hs_hwmod,
- &omap3xxx_usb_tll_hs_hwmod,
+/* 3430ES2+-only hwmod links */
+static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_dss__l3,
+ &omap3xxx_l4_core__dss,
+ &omap3xxx_usbhsotg__l3,
+ &omap3xxx_l4_core__usbhsotg,
+ &omap3xxx_usb_host_hs__l3_main_2,
+ &omap3xxx_l4_core__usb_host_hs,
+ &omap3xxx_l4_core__usb_tll_hs,
NULL
};
-/* <= 3430ES3-only hwmods */
-static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
- &omap3xxx_pre_es3_mmc1_hwmod,
- &omap3xxx_pre_es3_mmc2_hwmod,
+/* <= 3430ES3-only hwmod links */
+static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_l4_core__pre_es3_mmc1,
+ &omap3xxx_l4_core__pre_es3_mmc2,
NULL
};
-/* 3430ES3+-only hwmods */
-static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
- &omap3xxx_es3plus_mmc1_hwmod,
- &omap3xxx_es3plus_mmc2_hwmod,
+/* 3430ES3+-only hwmod links */
+static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_l4_core__es3plus_mmc1,
+ &omap3xxx_l4_core__es3plus_mmc2,
NULL
};
-/* 34xx-only hwmods (all ES revisions) */
-static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
- &omap3xxx_iva_hwmod,
- &omap34xx_sr1_hwmod,
- &omap34xx_sr2_hwmod,
- &omap3xxx_mailbox_hwmod,
+/* 34xx-only hwmod links (all ES revisions) */
+static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_l3__iva,
+ &omap34xx_l4_core__sr1,
+ &omap34xx_l4_core__sr2,
+ &omap3xxx_l4_core__mailbox,
+ &omap3xxx_l4_core__hdq1w,
NULL
};
-/* 36xx-only hwmods (all ES revisions) */
-static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
- &omap3xxx_iva_hwmod,
- &omap3xxx_uart4_hwmod,
- &omap3xxx_dss_core_hwmod,
- &omap36xx_sr1_hwmod,
- &omap36xx_sr2_hwmod,
- &omap3xxx_usbhsotg_hwmod,
- &omap3xxx_mailbox_hwmod,
- &omap3xxx_usb_host_hs_hwmod,
- &omap3xxx_usb_tll_hs_hwmod,
- &omap3xxx_es3plus_mmc1_hwmod,
- &omap3xxx_es3plus_mmc2_hwmod,
+/* 36xx-only hwmod links (all ES revisions) */
+static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_l3__iva,
+ &omap36xx_l4_per__uart4,
+ &omap3xxx_dss__l3,
+ &omap3xxx_l4_core__dss,
+ &omap36xx_l4_core__sr1,
+ &omap36xx_l4_core__sr2,
+ &omap3xxx_usbhsotg__l3,
+ &omap3xxx_l4_core__usbhsotg,
+ &omap3xxx_l4_core__mailbox,
+ &omap3xxx_usb_host_hs__l3_main_2,
+ &omap3xxx_l4_core__usb_host_hs,
+ &omap3xxx_l4_core__usb_tll_hs,
+ &omap3xxx_l4_core__es3plus_mmc1,
+ &omap3xxx_l4_core__es3plus_mmc2,
+ &omap3xxx_l4_core__hdq1w,
NULL
};
-static __initdata struct omap_hwmod *am35xx_hwmods[] = {
- &omap3xxx_dss_core_hwmod, /* XXX ??? */
- &am35xx_usbhsotg_hwmod,
- &am35xx_uart4_hwmod,
- &omap3xxx_usb_host_hs_hwmod,
- &omap3xxx_usb_tll_hs_hwmod,
- &omap3xxx_es3plus_mmc1_hwmod,
- &omap3xxx_es3plus_mmc2_hwmod,
+static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_dss__l3,
+ &omap3xxx_l4_core__dss,
+ &am35xx_usbhsotg__l3,
+ &am35xx_l4_core__usbhsotg,
+ &am35xx_l4_core__uart4,
+ &omap3xxx_usb_host_hs__l3_main_2,
+ &omap3xxx_l4_core__usb_host_hs,
+ &omap3xxx_l4_core__usb_tll_hs,
+ &omap3xxx_l4_core__es3plus_mmc1,
+ &omap3xxx_l4_core__es3plus_mmc2,
NULL
};
-static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
- /* dss class */
- &omap3xxx_dss_dispc_hwmod,
- &omap3xxx_dss_dsi1_hwmod,
- &omap3xxx_dss_rfbi_hwmod,
- &omap3xxx_dss_venc_hwmod,
+static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_l4_core__dss_dispc,
+ &omap3xxx_l4_core__dss_dsi1,
+ &omap3xxx_l4_core__dss_rfbi,
+ &omap3xxx_l4_core__dss_venc,
NULL
};
int __init omap3xxx_hwmod_init(void)
{
int r;
- struct omap_hwmod **h = NULL;
+ struct omap_hwmod_ocp_if **h = NULL;
unsigned int rev;
- /* Register hwmods common to all OMAP3 */
- r = omap_hwmod_register(omap3xxx_hwmods);
+ /* Register hwmod links common to all OMAP3 */
+ r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
if (r < 0)
return r;
- /* Register GP-only hwmods. */
+ /* Register GP-only hwmod links. */
if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
- r = omap_hwmod_register(omap3xxx_gp_hwmods);
+ r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
if (r < 0)
return r;
}
rev = omap_rev();
/*
- * Register hwmods common to individual OMAP3 families, all
+ * Register hwmod links common to individual OMAP3 families, all
* silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
* All possible revisions should be included in this conditional.
*/
if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
- h = omap34xx_hwmods;
+ h = omap34xx_hwmod_ocp_ifs;
} else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
- h = am35xx_hwmods;
+ h = am35xx_hwmod_ocp_ifs;
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
rev == OMAP3630_REV_ES1_2) {
- h = omap36xx_hwmods;
+ h = omap36xx_hwmod_ocp_ifs;
} else {
WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
return -EINVAL;
};
- r = omap_hwmod_register(h);
+ r = omap_hwmod_register_links(h);
if (r < 0)
return r;
/*
- * Register hwmods specific to certain ES levels of a
+ * Register hwmod links specific to certain ES levels of a
* particular family of silicon (e.g., 34xx ES1.0)
*/
h = NULL;
if (rev == OMAP3430_REV_ES1_0) {
- h = omap3430es1_hwmods;
+ h = omap3430es1_hwmod_ocp_ifs;
} else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
rev == OMAP3430_REV_ES3_1_2) {
- h = omap3430es2plus_hwmods;
+ h = omap3430es2plus_hwmod_ocp_ifs;
};
if (h) {
- r = omap_hwmod_register(h);
+ r = omap_hwmod_register_links(h);
if (r < 0)
return r;
}
h = NULL;
if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
rev == OMAP3430_REV_ES2_1) {
- h = omap3430_pre_es3_hwmods;
+ h = omap3430_pre_es3_hwmod_ocp_ifs;
} else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
rev == OMAP3430_REV_ES3_1_2) {
- h = omap3430_es3plus_hwmods;
+ h = omap3430_es3plus_hwmod_ocp_ifs;
};
if (h)
- r = omap_hwmod_register(h);
+ r = omap_hwmod_register_links(h);
if (r < 0)
return r;
/*
* DSS code presumes that dss_core hwmod is handled first,
* _before_ any other DSS related hwmods so register common
- * DSS hwmods last to ensure that dss_core is already registered.
- * Otherwise some change things may happen, for ex. if dispc
- * is handled before dss_core and DSS is enabled in bootloader
- * DIPSC will be reset with outputs enabled which sometimes leads
- * to unrecoverable L3 error.
- * XXX The long-term fix to this is to ensure modules are set up
- * in dependency order in the hwmod core code.
+ * DSS hwmod links last to ensure that dss_core is already
+ * registered. Otherwise some change things may happen, for
+ * ex. if dispc is handled before dss_core and DSS is enabled
+ * in bootloader DISPC will be reset with outputs enabled
+ * which sometimes leads to unrecoverable L3 error. XXX The
+ * long-term fix to this is to ensure hwmods are set up in
+ * dependency order in the hwmod core code.
*/
- r = omap_hwmod_register(omap3xxx_dss_hwmods);
+ r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
return r;
}
/*
* Hardware modules present on the OMAP44xx chips
*
- * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley
#define OMAP44XX_IRQ_GIC_START 32
/* Base offset for all OMAP4 dma requests */
-#define OMAP44XX_DMA_REQ_START 1
-
-/* Backward references (IPs with Bus Master capability) */
-static struct omap_hwmod omap44xx_aess_hwmod;
-static struct omap_hwmod omap44xx_dma_system_hwmod;
-static struct omap_hwmod omap44xx_dmm_hwmod;
-static struct omap_hwmod omap44xx_dsp_hwmod;
-static struct omap_hwmod omap44xx_dss_hwmod;
-static struct omap_hwmod omap44xx_emif_fw_hwmod;
-static struct omap_hwmod omap44xx_hsi_hwmod;
-static struct omap_hwmod omap44xx_ipu_hwmod;
-static struct omap_hwmod omap44xx_iss_hwmod;
-static struct omap_hwmod omap44xx_iva_hwmod;
-static struct omap_hwmod omap44xx_l3_instr_hwmod;
-static struct omap_hwmod omap44xx_l3_main_1_hwmod;
-static struct omap_hwmod omap44xx_l3_main_2_hwmod;
-static struct omap_hwmod omap44xx_l3_main_3_hwmod;
-static struct omap_hwmod omap44xx_l4_abe_hwmod;
-static struct omap_hwmod omap44xx_l4_cfg_hwmod;
-static struct omap_hwmod omap44xx_l4_per_hwmod;
-static struct omap_hwmod omap44xx_l4_wkup_hwmod;
-static struct omap_hwmod omap44xx_mmc1_hwmod;
-static struct omap_hwmod omap44xx_mmc2_hwmod;
-static struct omap_hwmod omap44xx_mpu_hwmod;
-static struct omap_hwmod omap44xx_mpu_private_hwmod;
-static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
-static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
-static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
+#define OMAP44XX_DMA_REQ_START 1
/*
- * Interconnects omap_hwmod structures
- * hwmods that compose the global OMAP interconnect
+ * IP blocks
*/
+/*
+ * 'c2c_target_fw' class
+ * instance(s): c2c_target_fw
+ */
+static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
+ .name = "c2c_target_fw",
+};
+
+/* c2c_target_fw */
+static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
+ .name = "c2c_target_fw",
+ .class = &omap44xx_c2c_target_fw_hwmod_class,
+ .clkdm_name = "d2d_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
+ },
+ },
+};
+
/*
* 'dmm' class
* instance(s): dmm
{ .irq = -1 }
};
-/* l3_main_1 -> dmm */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_dmm_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
- {
- .pa_start = 0x4e000000,
- .pa_end = 0x4e0007ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* mpu -> dmm */
-static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_dmm_hwmod,
- .clk = "l3_div_ck",
- .addr = omap44xx_dmm_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* dmm slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
- &omap44xx_l3_main_1__dmm,
- &omap44xx_mpu__dmm,
-};
-
static struct omap_hwmod omap44xx_dmm_hwmod = {
.name = "dmm",
.class = &omap44xx_dmm_hwmod_class,
.clkdm_name = "l3_emif_clkdm",
+ .mpu_irqs = omap44xx_dmm_irqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_dmm_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
- .mpu_irqs = omap44xx_dmm_irqs,
};
/*
};
/* emif_fw */
-/* dmm -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
- .master = &omap44xx_dmm_hwmod,
- .slave = &omap44xx_emif_fw_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
- {
- .pa_start = 0x4a20c000,
- .pa_end = 0x4a20c0ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_cfg -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_emif_fw_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_emif_fw_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* emif_fw slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
- &omap44xx_dmm__emif_fw,
- &omap44xx_l4_cfg__emif_fw,
-};
-
static struct omap_hwmod omap44xx_emif_fw_hwmod = {
.name = "emif_fw",
.class = &omap44xx_emif_fw_hwmod_class,
.context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_emif_fw_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
};
/*
};
/* l3_instr */
-/* iva -> l3_instr */
-static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
- .master = &omap44xx_iva_hwmod,
- .slave = &omap44xx_l3_instr_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_3 -> l3_instr */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
- .master = &omap44xx_l3_main_3_hwmod,
- .slave = &omap44xx_l3_instr_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_instr slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
- &omap44xx_iva__l3_instr,
- &omap44xx_l3_main_3__l3_instr,
-};
-
static struct omap_hwmod omap44xx_l3_instr_hwmod = {
.name = "l3_instr",
.class = &omap44xx_l3_hwmod_class,
.modulemode = MODULEMODE_HWCTRL,
},
},
- .slaves = omap44xx_l3_instr_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
};
/* l3_main_1 */
{ .irq = -1 }
};
-/* dsp -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
- .master = &omap44xx_dss_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc1 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
- .master = &omap44xx_mmc1_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc2 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
- .master = &omap44xx_mmc2_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
- {
- .pa_start = 0x44000000,
- .pa_end = 0x44000fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* mpu -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .addr = omap44xx_l3_main_1_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
- &omap44xx_dsp__l3_main_1,
- &omap44xx_dss__l3_main_1,
- &omap44xx_l3_main_2__l3_main_1,
- &omap44xx_l4_cfg__l3_main_1,
- &omap44xx_mmc1__l3_main_1,
- &omap44xx_mmc2__l3_main_1,
- &omap44xx_mpu__l3_main_1,
-};
-
static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
.name = "l3_main_1",
.class = &omap44xx_l3_hwmod_class,
.context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_l3_main_1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
};
/* l3_main_2 */
-/* dma_system -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
- .master = &omap44xx_dma_system_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* hsi -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
- .master = &omap44xx_hsi_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* ipu -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
- .master = &omap44xx_ipu_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* iss -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
- .master = &omap44xx_iss_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* iva -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
- .master = &omap44xx_iva_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
- {
- .pa_start = 0x44800000,
- .pa_end = 0x44801fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l3_main_1 -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .addr = omap44xx_l3_main_2_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* l4_cfg -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* usb_otg_hs -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
- .master = &omap44xx_usb_otg_hs_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
- &omap44xx_dma_system__l3_main_2,
- &omap44xx_hsi__l3_main_2,
- &omap44xx_ipu__l3_main_2,
- &omap44xx_iss__l3_main_2,
- &omap44xx_iva__l3_main_2,
- &omap44xx_l3_main_1__l3_main_2,
- &omap44xx_l4_cfg__l3_main_2,
- &omap44xx_usb_otg_hs__l3_main_2,
-};
-
static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
.name = "l3_main_2",
.class = &omap44xx_l3_hwmod_class,
.context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_l3_main_2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
};
/* l3_main_3 */
-static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
- {
- .pa_start = 0x45000000,
- .pa_end = 0x45000fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l3_main_1 -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_l3_main_3_hwmod,
- .clk = "l3_div_ck",
- .addr = omap44xx_l3_main_3_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_l3_main_3_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_l3_main_3_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
- &omap44xx_l3_main_1__l3_main_3,
- &omap44xx_l3_main_2__l3_main_3,
- &omap44xx_l4_cfg__l3_main_3,
-};
-
static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
.name = "l3_main_3",
.class = &omap44xx_l3_hwmod_class,
.modulemode = MODULEMODE_HWCTRL,
},
},
- .slaves = omap44xx_l3_main_3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
};
/*
};
/* l4_abe */
-/* aess -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
- .master = &omap44xx_aess_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dsp -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
- &omap44xx_aess__l4_abe,
- &omap44xx_dsp__l4_abe,
- &omap44xx_l3_main_1__l4_abe,
- &omap44xx_mpu__l4_abe,
-};
-
static struct omap_hwmod omap44xx_l4_abe_hwmod = {
.name = "l4_abe",
.class = &omap44xx_l4_hwmod_class,
.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
},
},
- .slaves = omap44xx_l4_abe_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
};
/* l4_cfg */
-/* l3_main_1 -> l4_cfg */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_l4_cfg_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
- &omap44xx_l3_main_1__l4_cfg,
-};
-
static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
.name = "l4_cfg",
.class = &omap44xx_l4_hwmod_class,
.context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_l4_cfg_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
};
/* l4_per */
-/* l3_main_2 -> l4_per */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_l4_per_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
- &omap44xx_l3_main_2__l4_per,
-};
-
static struct omap_hwmod omap44xx_l4_per_hwmod = {
.name = "l4_per",
.class = &omap44xx_l4_hwmod_class,
.context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_l4_per_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
};
/* l4_wkup */
-/* l4_cfg -> l4_wkup */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_l4_wkup_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
- &omap44xx_l4_cfg__l4_wkup,
-};
-
static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
.name = "l4_wkup",
.class = &omap44xx_l4_hwmod_class,
.context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_l4_wkup_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
};
/*
};
/* mpu_private */
-/* mpu -> mpu_private */
-static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_mpu_private_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu_private slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
- &omap44xx_mpu__mpu_private,
-};
-
static struct omap_hwmod omap44xx_mpu_private_hwmod = {
.name = "mpu_private",
.class = &omap44xx_mpu_bus_hwmod_class,
.clkdm_name = "mpuss_clkdm",
- .slaves = omap44xx_mpu_private_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
+};
+
+/*
+ * 'ocp_wp_noc' class
+ * instance(s): ocp_wp_noc
+ */
+static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
+ .name = "ocp_wp_noc",
+};
+
+/* ocp_wp_noc */
+static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
+ .name = "ocp_wp_noc",
+ .class = &omap44xx_ocp_wp_noc_hwmod_class,
+ .clkdm_name = "l3_instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
};
/*
* - They still need to be validated with the driver
* properly adapted to omap_hwmod / omap_device
*
- * c2c
- * c2c_target_fw
- * cm_core
- * cm_core_aon
- * ctrl_module_core
- * ctrl_module_pad_core
- * ctrl_module_pad_wkup
- * ctrl_module_wkup
- * debugss
- * efuse_ctrl_cust
- * efuse_ctrl_std
- * elm
- * emif1
- * emif2
- * fdif
- * gpmc
- * gpu
- * hdq1w
- * mcasp
- * mpu_c0
- * mpu_c1
- * ocmc_ram
- * ocp2scp_usb_phy
- * ocp_wp_noc
- * prcm_mpu
- * prm
- * scrm
- * sl2if
- * slimbus1
- * slimbus2
- * usb_host_fs
- * usb_host_hs
- * usb_phy_cm
- * usb_tll_hs
- * usim
+ * usim
*/
/*
{ .dma_req = -1 }
};
-/* aess master ports */
-static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
- &omap44xx_aess__l4_abe,
-};
-
-static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
- {
- .pa_start = 0x401f1000,
- .pa_end = 0x401f13ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> aess */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_aess_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_aess_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
- {
- .pa_start = 0x490f1000,
- .pa_end = 0x490f13ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> aess (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_aess_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_aess_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* aess slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
- &omap44xx_l4_abe__aess,
- &omap44xx_l4_abe__aess_dma,
-};
-
static struct omap_hwmod omap44xx_aess_hwmod = {
.name = "aess",
.class = &omap44xx_aess_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_aess_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
- .masters = omap44xx_aess_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
};
/*
- * 'bandgap' class
- * bangap reference for ldo regulators
+ * 'c2c' class
+ * chip 2 chip interface used to plug the ape soc (omap) with an external modem
+ * soc
*/
-static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
- .name = "bandgap",
+static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
+ .name = "c2c",
+};
+
+/* c2c */
+static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
+ { .irq = 88 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
-/* bandgap */
-static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
- { .role = "fclk", .clk = "bandgap_fclk" },
+static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
+ { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
-static struct omap_hwmod omap44xx_bandgap_hwmod = {
- .name = "bandgap",
- .class = &omap44xx_bandgap_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
+static struct omap_hwmod omap44xx_c2c_hwmod = {
+ .name = "c2c",
+ .class = &omap44xx_c2c_hwmod_class,
+ .clkdm_name = "d2d_clkdm",
+ .mpu_irqs = omap44xx_c2c_irqs,
+ .sdma_reqs = omap44xx_c2c_sdma_reqs,
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
+ .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
},
},
- .opt_clks = bandgap_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
};
/*
};
/* counter_32k */
-static struct omap_hwmod omap44xx_counter_32k_hwmod;
-static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
- {
- .pa_start = 0x4a304000,
- .pa_end = 0x4a30401f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_wkup -> counter_32k */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_counter_32k_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_counter_32k_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* counter_32k slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
- &omap44xx_l4_wkup__counter_32k,
-};
-
static struct omap_hwmod omap44xx_counter_32k_hwmod = {
.name = "counter_32k",
.class = &omap44xx_counter_hwmod_class,
.context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_counter_32k_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
+};
+
+/*
+ * 'ctrl_module' class
+ * attila core control module + core pad control module + wkup pad control
+ * module + attila wkup control module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
+ .name = "ctrl_module",
+ .sysc = &omap44xx_ctrl_module_sysc,
+};
+
+/* ctrl_module_core */
+static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
+ { .irq = 8 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
+ .name = "ctrl_module_core",
+ .class = &omap44xx_ctrl_module_hwmod_class,
+ .clkdm_name = "l4_cfg_clkdm",
+ .mpu_irqs = omap44xx_ctrl_module_core_irqs,
+};
+
+/* ctrl_module_pad_core */
+static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
+ .name = "ctrl_module_pad_core",
+ .class = &omap44xx_ctrl_module_hwmod_class,
+ .clkdm_name = "l4_cfg_clkdm",
+};
+
+/* ctrl_module_wkup */
+static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
+ .name = "ctrl_module_wkup",
+ .class = &omap44xx_ctrl_module_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+};
+
+/* ctrl_module_pad_wkup */
+static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
+ .name = "ctrl_module_pad_wkup",
+ .class = &omap44xx_ctrl_module_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+};
+
+/*
+ * 'debugss' class
+ * debug and emulation sub system
+ */
+
+static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
+ .name = "debugss",
+};
+
+/* debugss */
+static struct omap_hwmod omap44xx_debugss_hwmod = {
+ .name = "debugss",
+ .class = &omap44xx_debugss_hwmod_class,
+ .clkdm_name = "emu_sys_clkdm",
+ .main_clk = "trace_clk_div_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
+ },
+ },
};
/*
{ .irq = -1 }
};
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
- &omap44xx_dma_system__l3_main_2,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
- {
- .pa_start = 0x4a056000,
- .pa_end = 0x4a056fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_dma_system_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_dma_system_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
- &omap44xx_l4_cfg__dma_system,
-};
-
-static struct omap_hwmod omap44xx_dma_system_hwmod = {
- .name = "dma_system",
- .class = &omap44xx_dma_hwmod_class,
- .clkdm_name = "l3_dma_clkdm",
- .mpu_irqs = omap44xx_dma_system_irqs,
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
- },
- },
- .dev_attr = &dma_dev_attr,
- .slaves = omap44xx_dma_system_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
- .masters = omap44xx_dma_system_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
+static struct omap_hwmod omap44xx_dma_system_hwmod = {
+ .name = "dma_system",
+ .class = &omap44xx_dma_hwmod_class,
+ .clkdm_name = "l3_dma_clkdm",
+ .mpu_irqs = omap44xx_dma_system_irqs,
+ .main_clk = "l3_div_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
+ },
+ },
+ .dev_attr = &dma_dev_attr,
};
/*
};
/* dmic */
-static struct omap_hwmod omap44xx_dmic_hwmod;
static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
{ .irq = 114 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x4012e000,
- .pa_end = 0x4012e07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> dmic */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_dmic_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_dmic_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
- {
- .name = "dma",
- .pa_start = 0x4902e000,
- .pa_end = 0x4902e07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> dmic (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_dmic_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_dmic_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* dmic slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
- &omap44xx_l4_abe__dmic,
- &omap44xx_l4_abe__dmic_dma,
-};
-
static struct omap_hwmod omap44xx_dmic_hwmod = {
.name = "dmic",
.class = &omap44xx_dmic_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_dmic_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
};
/*
};
static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
- { .name = "mmu_cache", .rst_shift = 1 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
{ .name = "dsp", .rst_shift = 0 },
-};
-
-/* dsp -> iva */
-static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_iva_hwmod,
- .clk = "dpll_iva_m5x2_ck",
-};
-
-/* dsp master ports */
-static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
- &omap44xx_dsp__l3_main_1,
- &omap44xx_dsp__l4_abe,
- &omap44xx_dsp__iva,
-};
-
-/* l4_cfg -> dsp */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_dsp_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dsp slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
- &omap44xx_l4_cfg__dsp,
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
- .name = "dsp_c0",
- .class = &omap44xx_dsp_hwmod_class,
- .clkdm_name = "tesla_clkdm",
- .flags = HWMOD_INIT_NO_RESET,
- .rst_lines = omap44xx_dsp_c0_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
- .prcm = {
- .omap4 = {
- .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
- },
- },
+ { .name = "mmu_cache", .rst_shift = 1 },
};
static struct omap_hwmod omap44xx_dsp_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .slaves = omap44xx_dsp_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
- .masters = omap44xx_dsp_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
};
/*
};
/* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
- &omap44xx_dss__l3_main_1,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
- {
- .pa_start = 0x58000000,
- .pa_end = 0x5800007f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l3_main_2 -> dss */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_hwmod,
- .clk = "dss_fck",
- .addr = omap44xx_dss_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
- {
- .pa_start = 0x48040000,
- .pa_end = 0x4804007f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> dss */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_dss_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
- &omap44xx_l3_main_2__dss,
- &omap44xx_l4_per__dss,
-};
-
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
{ .role = "tv_clk", .clk = "dss_tv_clk" },
},
.opt_clks = dss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
- .slaves = omap44xx_dss_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
- .masters = omap44xx_dss_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
};
/*
};
/* dss_dispc */
-static struct omap_hwmod omap44xx_dss_dispc_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
{ .irq = 25 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
- {
- .pa_start = 0x58001000,
- .pa_end = 0x58001fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l3_main_2 -> dss_dispc */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_dispc_hwmod,
- .clk = "dss_fck",
- .addr = omap44xx_dss_dispc_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
- {
- .pa_start = 0x48041000,
- .pa_end = 0x48041fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
.manager_count = 3,
.has_framedonetv_irq = 1
};
-/* l4_per -> dss_dispc */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_dispc_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_dss_dispc_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
- &omap44xx_l3_main_2__dss_dispc,
- &omap44xx_l4_per__dss_dispc,
-};
-
static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &omap44xx_dispc_hwmod_class,
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_dss_dispc_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
.dev_attr = &omap44xx_dss_dispc_dev_attr
};
};
/* dss_dsi1 */
-static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
{ .irq = 53 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
- {
- .pa_start = 0x58004000,
- .pa_end = 0x580041ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l3_main_2 -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_dsi1_hwmod,
- .clk = "dss_fck",
- .addr = omap44xx_dss_dsi1_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
- {
- .pa_start = 0x48044000,
- .pa_end = 0x480441ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_dsi1_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_dss_dsi1_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* dss_dsi1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
- &omap44xx_l3_main_2__dss_dsi1,
- &omap44xx_l4_per__dss_dsi1,
-};
-
static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
},
.opt_clks = dss_dsi1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
- .slaves = omap44xx_dss_dsi1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
};
/* dss_dsi2 */
-static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
{ .irq = 84 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
- {
- .pa_start = 0x58005000,
- .pa_end = 0x580051ff,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
+ { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+
+static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+ .name = "dss_dsi2",
+ .class = &omap44xx_dsi_hwmod_class,
+ .clkdm_name = "l3_dss_clkdm",
+ .mpu_irqs = omap44xx_dss_dsi2_irqs,
+ .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+ },
},
- { }
-};
-
-/* l3_main_2 -> dss_dsi2 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_dsi2_hwmod,
- .clk = "dss_fck",
- .addr = omap44xx_dss_dsi2_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
- {
- .pa_start = 0x48045000,
- .pa_end = 0x480451ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> dss_dsi2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_dsi2_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_dss_dsi2_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* dss_dsi2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
- &omap44xx_l3_main_2__dss_dsi2,
- &omap44xx_l4_per__dss_dsi2,
-};
-
-static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
- .name = "dss_dsi2",
- .class = &omap44xx_dsi_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .mpu_irqs = omap44xx_dss_dsi2_irqs,
- .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .opt_clks = dss_dsi2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
- .slaves = omap44xx_dss_dsi2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
+ .opt_clks = dss_dsi2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
};
/*
};
/* dss_hdmi */
-static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
{ .irq = 101 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
- {
- .pa_start = 0x58006000,
- .pa_end = 0x58006fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l3_main_2 -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_hdmi_hwmod,
- .clk = "dss_fck",
- .addr = omap44xx_dss_hdmi_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
- {
- .pa_start = 0x48046000,
- .pa_end = 0x48046fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_hdmi_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_dss_hdmi_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* dss_hdmi slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
- &omap44xx_l3_main_2__dss_hdmi,
- &omap44xx_l4_per__dss_hdmi,
-};
-
static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
},
.opt_clks = dss_hdmi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
- .slaves = omap44xx_dss_hdmi_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
};
/*
};
/* dss_rfbi */
-static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
{ .dma_req = 13 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
- {
- .pa_start = 0x58002000,
- .pa_end = 0x580020ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l3_main_2 -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_rfbi_hwmod,
- .clk = "dss_fck",
- .addr = omap44xx_dss_rfbi_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
- {
- .pa_start = 0x48042000,
- .pa_end = 0x480420ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_rfbi_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_dss_rfbi_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
- &omap44xx_l3_main_2__dss_rfbi,
- &omap44xx_l4_per__dss_rfbi,
-};
-
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
{ .role = "ick", .clk = "dss_fck" },
};
},
.opt_clks = dss_rfbi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
- .slaves = omap44xx_dss_rfbi_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
};
/*
};
/* dss_venc */
-static struct omap_hwmod omap44xx_dss_venc_hwmod;
-static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
- {
- .pa_start = 0x58003000,
- .pa_end = 0x580030ff,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+ .name = "dss_venc",
+ .class = &omap44xx_venc_hwmod_class,
+ .clkdm_name = "l3_dss_clkdm",
+ .main_clk = "dss_tv_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+ },
},
- { }
};
-/* l3_main_2 -> dss_venc */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_venc_hwmod,
- .clk = "dss_fck",
- .addr = omap44xx_dss_venc_dma_addrs,
- .user = OCP_USER_SDMA,
+/*
+ * 'elm' class
+ * bch error location module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
};
-static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
- {
- .pa_start = 0x48043000,
- .pa_end = 0x480430ff,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
+ .name = "elm",
+ .sysc = &omap44xx_elm_sysc,
+};
+
+/* elm */
+static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
+ { .irq = 4 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_elm_hwmod = {
+ .name = "elm",
+ .class = &omap44xx_elm_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_elm_irqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
+ },
},
- { }
};
-/* l4_per -> dss_venc */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_venc_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_dss_venc_addrs,
- .user = OCP_USER_MPU,
+/*
+ * 'emif' class
+ * external memory interface no1
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
+ .rev_offs = 0x0000,
};
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
- &omap44xx_l3_main_2__dss_venc,
- &omap44xx_l4_per__dss_venc,
+static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
+ .name = "emif",
+ .sysc = &omap44xx_emif_sysc,
};
-static struct omap_hwmod omap44xx_dss_venc_hwmod = {
- .name = "dss_venc",
- .class = &omap44xx_venc_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_tv_clk",
+/* emif1 */
+static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
+ { .irq = 110 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_emif1_hwmod = {
+ .name = "emif1",
+ .class = &omap44xx_emif_hwmod_class,
+ .clkdm_name = "l3_emif_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_emif1_irqs,
+ .main_clk = "ddrphy_ck",
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+ .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* emif2 */
+static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
+ { .irq = 111 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_emif2_hwmod = {
+ .name = "emif2",
+ .class = &omap44xx_emif_hwmod_class,
+ .clkdm_name = "l3_emif_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_emif2_irqs,
+ .main_clk = "ddrphy_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'fdif' class
+ * face detection hw accelerator module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ /*
+ * FDIF needs 100 OCP clk cycles delay after a softreset before
+ * accessing sysconfig again.
+ * The lowest frequency at the moment for L3 bus is 100 MHz, so
+ * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
+ *
+ * TODO: Indicate errata when available.
+ */
+ .srst_udelay = 2,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
+ .name = "fdif",
+ .sysc = &omap44xx_fdif_sysc,
+};
+
+/* fdif */
+static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
+ { .irq = 69 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_fdif_hwmod = {
+ .name = "fdif",
+ .class = &omap44xx_fdif_hwmod_class,
+ .clkdm_name = "iss_clkdm",
+ .mpu_irqs = omap44xx_fdif_irqs,
+ .main_clk = "fdif_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_dss_venc_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
};
/*
};
/* gpio1 */
-static struct omap_hwmod omap44xx_gpio1_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
- {
- .pa_start = 0x4a310000,
- .pa_end = 0x4a3101ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_gpio1_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_gpio1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
- &omap44xx_l4_wkup__gpio1,
-};
-
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
};
.opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
.dev_attr = &gpio_dev_attr,
- .slaves = omap44xx_gpio1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
};
/* gpio2 */
-static struct omap_hwmod omap44xx_gpio2_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
- {
- .pa_start = 0x48055000,
- .pa_end = 0x480551ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> gpio2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_gpio2_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_gpio2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
- &omap44xx_l4_per__gpio2,
-};
-
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbclk" },
};
.opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
.dev_attr = &gpio_dev_attr,
- .slaves = omap44xx_gpio2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
};
/* gpio3 */
-static struct omap_hwmod omap44xx_gpio3_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
- {
- .pa_start = 0x48057000,
- .pa_end = 0x480571ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> gpio3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_gpio3_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_gpio3_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
- &omap44xx_l4_per__gpio3,
-};
-
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbclk" },
};
.opt_clks = gpio3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
.dev_attr = &gpio_dev_attr,
- .slaves = omap44xx_gpio3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
};
/* gpio4 */
-static struct omap_hwmod omap44xx_gpio4_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
- {
- .pa_start = 0x48059000,
- .pa_end = 0x480591ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> gpio4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_gpio4_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_gpio4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
- &omap44xx_l4_per__gpio4,
-};
-
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio4_dbclk" },
};
.opt_clks = gpio4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
.dev_attr = &gpio_dev_attr,
- .slaves = omap44xx_gpio4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
};
/* gpio5 */
-static struct omap_hwmod omap44xx_gpio5_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
- {
- .pa_start = 0x4805b000,
- .pa_end = 0x4805b1ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> gpio5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_gpio5_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_gpio5_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio5 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
- &omap44xx_l4_per__gpio5,
-};
-
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio5_dbclk" },
};
.opt_clks = gpio5_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
.dev_attr = &gpio_dev_attr,
- .slaves = omap44xx_gpio5_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
};
/* gpio6 */
-static struct omap_hwmod omap44xx_gpio6_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
- {
- .pa_start = 0x4805d000,
- .pa_end = 0x4805d1ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> gpio6 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_gpio6_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_gpio6_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio6 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
- &omap44xx_l4_per__gpio6,
-};
-
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio6_dbclk" },
};
.opt_clks = gpio6_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
.dev_attr = &gpio_dev_attr,
- .slaves = omap44xx_gpio6_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
+};
+
+/*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
+ .name = "gpmc",
+ .sysc = &omap44xx_gpmc_sysc,
+};
+
+/* gpmc */
+static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
+ { .irq = 20 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
+ { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap44xx_gpmc_hwmod = {
+ .name = "gpmc",
+ .class = &omap44xx_gpmc_hwmod_class,
+ .clkdm_name = "l3_2_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_gpmc_irqs,
+ .sdma_reqs = omap44xx_gpmc_sdma_reqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'gpu' class
+ * 2d/3d graphics accelerator
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
+ .rev_offs = 0x1fc00,
+ .sysc_offs = 0x1fc10,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
+ .name = "gpu",
+ .sysc = &omap44xx_gpu_sysc,
+};
+
+/* gpu */
+static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
+ { .irq = 21 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_gpu_hwmod = {
+ .name = "gpu",
+ .class = &omap44xx_gpu_hwmod_class,
+ .clkdm_name = "l3_gfx_clkdm",
+ .mpu_irqs = omap44xx_gpu_irqs,
+ .main_clk = "gpu_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'hdq1w' class
+ * hdq / 1-wire serial interface controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0014,
+ .syss_offs = 0x0018,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
+ .name = "hdq1w",
+ .sysc = &omap44xx_hdq1w_sysc,
+};
+
+/* hdq1w */
+static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
+ { .irq = 58 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_hdq1w_hwmod = {
+ .name = "hdq1w",
+ .class = &omap44xx_hdq1w_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
+ .mpu_irqs = omap44xx_hdq1w_irqs,
+ .main_clk = "hdq1w_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
};
/*
{ .irq = -1 }
};
-/* hsi master ports */
-static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
- &omap44xx_hsi__l3_main_2,
-};
-
-static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
- {
- .pa_start = 0x4a058000,
- .pa_end = 0x4a05bfff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_cfg -> hsi */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_hsi_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_hsi_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* hsi slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
- &omap44xx_l4_cfg__hsi,
-};
-
static struct omap_hwmod omap44xx_hsi_hwmod = {
.name = "hsi",
.class = &omap44xx_hsi_hwmod_class,
.modulemode = MODULEMODE_HWCTRL,
},
},
- .slaves = omap44xx_hsi_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
- .masters = omap44xx_hsi_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
};
/*
};
static struct omap_i2c_dev_attr i2c_dev_attr = {
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
};
/* i2c1 */
-static struct omap_hwmod omap44xx_i2c1_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
- {
- .pa_start = 0x48070000,
- .pa_end = 0x480700ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> i2c1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_i2c1_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_i2c1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* i2c1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
- &omap44xx_l4_per__i2c1,
-};
-
static struct omap_hwmod omap44xx_i2c1_hwmod = {
.name = "i2c1",
.class = &omap44xx_i2c_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_i2c1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
.dev_attr = &i2c_dev_attr,
};
/* i2c2 */
-static struct omap_hwmod omap44xx_i2c2_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
- {
- .pa_start = 0x48072000,
- .pa_end = 0x480720ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> i2c2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_i2c2_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_i2c2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* i2c2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
- &omap44xx_l4_per__i2c2,
-};
-
static struct omap_hwmod omap44xx_i2c2_hwmod = {
.name = "i2c2",
.class = &omap44xx_i2c_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_i2c2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
.dev_attr = &i2c_dev_attr,
};
/* i2c3 */
-static struct omap_hwmod omap44xx_i2c3_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
- {
- .pa_start = 0x48060000,
- .pa_end = 0x480600ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> i2c3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_i2c3_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_i2c3_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* i2c3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
- &omap44xx_l4_per__i2c3,
-};
-
static struct omap_hwmod omap44xx_i2c3_hwmod = {
.name = "i2c3",
.class = &omap44xx_i2c_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_i2c3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
.dev_attr = &i2c_dev_attr,
};
/* i2c4 */
-static struct omap_hwmod omap44xx_i2c4_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
- {
- .pa_start = 0x48350000,
- .pa_end = 0x483500ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> i2c4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_i2c4_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_i2c4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* i2c4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
- &omap44xx_l4_per__i2c4,
-};
-
static struct omap_hwmod omap44xx_i2c4_hwmod = {
.name = "i2c4",
.class = &omap44xx_i2c_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_i2c4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
.dev_attr = &i2c_dev_attr,
};
{ .irq = -1 }
};
-static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
+static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
{ .name = "cpu0", .rst_shift = 0 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
{ .name = "cpu1", .rst_shift = 1 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
{ .name = "mmu_cache", .rst_shift = 2 },
};
-/* ipu master ports */
-static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
- &omap44xx_ipu__l3_main_2,
-};
-
-/* l3_main_2 -> ipu */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_ipu_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* ipu slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
- &omap44xx_l3_main_2__ipu,
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
- .name = "ipu_c0",
- .class = &omap44xx_ipu_hwmod_class,
- .clkdm_name = "ducati_clkdm",
- .flags = HWMOD_INIT_NO_RESET,
- .rst_lines = omap44xx_ipu_c0_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
- .prcm = {
- .omap4 = {
- .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
- },
- },
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
- .name = "ipu_c1",
- .class = &omap44xx_ipu_hwmod_class,
- .clkdm_name = "ducati_clkdm",
- .flags = HWMOD_INIT_NO_RESET,
- .rst_lines = omap44xx_ipu_c1_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
- .prcm = {
- .omap4 = {
- .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
- },
- },
-};
-
static struct omap_hwmod omap44xx_ipu_hwmod = {
.name = "ipu",
.class = &omap44xx_ipu_hwmod_class,
.modulemode = MODULEMODE_HWCTRL,
},
},
- .slaves = omap44xx_ipu_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
- .masters = omap44xx_ipu_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
};
/*
{ .dma_req = -1 }
};
-/* iss master ports */
-static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
- &omap44xx_iss__l3_main_2,
-};
-
-static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
- {
- .pa_start = 0x52000000,
- .pa_end = 0x520000ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l3_main_2 -> iss */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_iss_hwmod,
- .clk = "l3_div_ck",
- .addr = omap44xx_iss_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* iss slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
- &omap44xx_l3_main_2__iss,
-};
-
static struct omap_hwmod_opt_clk iss_opt_clks[] = {
{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
};
},
.opt_clks = iss_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
- .slaves = omap44xx_iss_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
- .masters = omap44xx_iss_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
};
/*
};
static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
- { .name = "logic", .rst_shift = 2 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
{ .name = "seq0", .rst_shift = 0 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
{ .name = "seq1", .rst_shift = 1 },
-};
-
-/* iva master ports */
-static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
- &omap44xx_iva__l3_main_2,
- &omap44xx_iva__l3_instr,
-};
-
-static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
- {
- .pa_start = 0x5a000000,
- .pa_end = 0x5a07ffff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l3_main_2 -> iva */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_iva_hwmod,
- .clk = "l3_div_ck",
- .addr = omap44xx_iva_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* iva slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
- &omap44xx_dsp__iva,
- &omap44xx_l3_main_2__iva,
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
- .name = "iva_seq0",
- .class = &omap44xx_iva_hwmod_class,
- .clkdm_name = "ivahd_clkdm",
- .flags = HWMOD_INIT_NO_RESET,
- .rst_lines = omap44xx_iva_seq0_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
- .prcm = {
- .omap4 = {
- .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
- },
- },
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
- .name = "iva_seq1",
- .class = &omap44xx_iva_hwmod_class,
- .clkdm_name = "ivahd_clkdm",
- .flags = HWMOD_INIT_NO_RESET,
- .rst_lines = omap44xx_iva_seq1_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
- .prcm = {
- .omap4 = {
- .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
- },
- },
+ { .name = "logic", .rst_shift = 2 },
};
static struct omap_hwmod omap44xx_iva_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
- .slaves = omap44xx_iva_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
- .masters = omap44xx_iva_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
};
/*
};
/* kbd */
-static struct omap_hwmod omap44xx_kbd_hwmod;
static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
{ .irq = 120 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
- {
- .pa_start = 0x4a31c000,
- .pa_end = 0x4a31c07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_wkup -> kbd */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_kbd_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_kbd_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* kbd slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
- &omap44xx_l4_wkup__kbd,
-};
-
static struct omap_hwmod omap44xx_kbd_hwmod = {
.name = "kbd",
.class = &omap44xx_kbd_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_kbd_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
};
/*
};
/* mailbox */
-static struct omap_hwmod omap44xx_mailbox_hwmod;
static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
{ .irq = 26 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
- {
- .pa_start = 0x4a0f4000,
- .pa_end = 0x4a0f41ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_cfg -> mailbox */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_mailbox_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mailbox_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
- &omap44xx_l4_cfg__mailbox,
-};
-
static struct omap_hwmod omap44xx_mailbox_hwmod = {
.name = "mailbox",
.class = &omap44xx_mailbox_hwmod_class,
.context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_mailbox_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
+};
+
+/*
+ * 'mcasp' class
+ * multi-channel audio serial port controller
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
+ .sidle_shift = 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
+ .sysc_offs = 0x0004,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type_mcasp,
+};
+
+static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
+ .name = "mcasp",
+ .sysc = &omap44xx_mcasp_sysc,
+};
+
+/* mcasp */
+static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
+ { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
+ { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
+ { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
+ { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap44xx_mcasp_hwmod = {
+ .name = "mcasp",
+ .class = &omap44xx_mcasp_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_mcasp_irqs,
+ .sdma_reqs = omap44xx_mcasp_sdma_reqs,
+ .main_clk = "mcasp_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
};
/*
};
/* mcbsp1 */
-static struct omap_hwmod omap44xx_mcbsp1_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
- { .irq = 17 + OMAP44XX_IRQ_GIC_START },
+ { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x40122000,
- .pa_end = 0x401220ff,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
+ { .role = "pad_fck", .clk = "pad_clks_ck" },
+ { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap44xx_mcbsp_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_mcbsp1_irqs,
+ .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
+ .main_clk = "mcbsp1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
},
- { }
-};
-
-/* l4_abe -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp1_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp1_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
- {
- .name = "dma",
- .pa_start = 0x49022000,
- .pa_end = 0x490220ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> mcbsp1 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp1_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp1_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
- &omap44xx_l4_abe__mcbsp1,
- &omap44xx_l4_abe__mcbsp1_dma,
-};
-
-static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap44xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_mcbsp1_irqs,
- .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
- .main_clk = "mcbsp1_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .slaves = omap44xx_mcbsp1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
- .opt_clks = mcbsp1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
+ .opt_clks = mcbsp1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
};
/* mcbsp2 */
-static struct omap_hwmod omap44xx_mcbsp2_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
- { .irq = 22 + OMAP44XX_IRQ_GIC_START },
+ { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x40124000,
- .pa_end = 0x401240ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp2_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp2_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
- {
- .name = "dma",
- .pa_start = 0x49024000,
- .pa_end = 0x490240ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> mcbsp2 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp2_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp2_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
- &omap44xx_l4_abe__mcbsp2,
- &omap44xx_l4_abe__mcbsp2_dma,
-};
-
static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_mcbsp2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
.opt_clks = mcbsp2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
};
/* mcbsp3 */
-static struct omap_hwmod omap44xx_mcbsp3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
- { .irq = 23 + OMAP44XX_IRQ_GIC_START },
+ { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x40126000,
- .pa_end = 0x401260ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp3_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp3_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
- {
- .name = "dma",
- .pa_start = 0x49026000,
- .pa_end = 0x490260ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> mcbsp3 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp3_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp3_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* mcbsp3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
- &omap44xx_l4_abe__mcbsp3,
- &omap44xx_l4_abe__mcbsp3_dma,
-};
-
static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_mcbsp3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
.opt_clks = mcbsp3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
};
/* mcbsp4 */
-static struct omap_hwmod omap44xx_mcbsp4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
- { .irq = 16 + OMAP44XX_IRQ_GIC_START },
+ { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
- {
- .pa_start = 0x48096000,
- .pa_end = 0x480960ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mcbsp4_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mcbsp4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
- &omap44xx_l4_per__mcbsp4,
-};
-
static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_mcbsp4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
.opt_clks = mcbsp4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
};
};
/* mcpdm */
-static struct omap_hwmod omap44xx_mcpdm_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
{ .irq = 112 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
- {
- .pa_start = 0x40132000,
- .pa_end = 0x4013207f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> mcpdm */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcpdm_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_mcpdm_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
- {
- .pa_start = 0x49032000,
- .pa_end = 0x4903207f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> mcpdm (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcpdm_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_mcpdm_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* mcpdm slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
- &omap44xx_l4_abe__mcpdm,
- &omap44xx_l4_abe__mcpdm_dma,
-};
-
static struct omap_hwmod omap44xx_mcpdm_hwmod = {
.name = "mcpdm",
.class = &omap44xx_mcpdm_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_mcpdm_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
};
/*
};
/* mcspi1 */
-static struct omap_hwmod omap44xx_mcspi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
- {
- .pa_start = 0x48098000,
- .pa_end = 0x480981ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> mcspi1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mcspi1_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mcspi1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcspi1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
- &omap44xx_l4_per__mcspi1,
-};
-
/* mcspi1 dev_attr */
static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
.num_chipselect = 4,
},
},
.dev_attr = &mcspi1_dev_attr,
- .slaves = omap44xx_mcspi1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
};
/* mcspi2 */
-static struct omap_hwmod omap44xx_mcspi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
- {
- .pa_start = 0x4809a000,
- .pa_end = 0x4809a1ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> mcspi2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mcspi2_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mcspi2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcspi2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
- &omap44xx_l4_per__mcspi2,
-};
-
/* mcspi2 dev_attr */
static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
.num_chipselect = 2,
},
},
.dev_attr = &mcspi2_dev_attr,
- .slaves = omap44xx_mcspi2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
};
/* mcspi3 */
-static struct omap_hwmod omap44xx_mcspi3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
- {
- .pa_start = 0x480b8000,
- .pa_end = 0x480b81ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> mcspi3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mcspi3_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mcspi3_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcspi3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
- &omap44xx_l4_per__mcspi3,
-};
-
-/* mcspi3 dev_attr */
-static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
- .num_chipselect = 2,
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+ .num_chipselect = 2,
};
static struct omap_hwmod omap44xx_mcspi3_hwmod = {
},
},
.dev_attr = &mcspi3_dev_attr,
- .slaves = omap44xx_mcspi3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
};
/* mcspi4 */
-static struct omap_hwmod omap44xx_mcspi4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
- {
- .pa_start = 0x480ba000,
- .pa_end = 0x480ba1ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> mcspi4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mcspi4_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mcspi4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcspi4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
- &omap44xx_l4_per__mcspi4,
-};
-
/* mcspi4 dev_attr */
static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
.num_chipselect = 1,
},
},
.dev_attr = &mcspi4_dev_attr,
- .slaves = omap44xx_mcspi4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
};
/*
{ .dma_req = -1 }
};
-/* mmc1 master ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
- &omap44xx_mmc1__l3_main_1,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
- {
- .pa_start = 0x4809c000,
- .pa_end = 0x4809c3ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> mmc1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mmc1_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mmc1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
- &omap44xx_l4_per__mmc1,
-};
-
/* mmc1 dev_attr */
static struct omap_mmc_dev_attr mmc1_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
},
},
.dev_attr = &mmc1_dev_attr,
- .slaves = omap44xx_mmc1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
- .masters = omap44xx_mmc1_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
};
/* mmc2 */
{ .dma_req = -1 }
};
-/* mmc2 master ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
- &omap44xx_mmc2__l3_main_1,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
- {
- .pa_start = 0x480b4000,
- .pa_end = 0x480b43ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> mmc2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mmc2_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mmc2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
- &omap44xx_l4_per__mmc2,
-};
-
static struct omap_hwmod omap44xx_mmc2_hwmod = {
.name = "mmc2",
.class = &omap44xx_mmc_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_mmc2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
- .masters = omap44xx_mmc2_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
};
/* mmc3 */
-static struct omap_hwmod omap44xx_mmc3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
{ .irq = 94 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
- {
- .pa_start = 0x480ad000,
- .pa_end = 0x480ad3ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> mmc3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mmc3_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mmc3_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
- &omap44xx_l4_per__mmc3,
-};
-
static struct omap_hwmod omap44xx_mmc3_hwmod = {
.name = "mmc3",
.class = &omap44xx_mmc_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_mmc3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
};
/* mmc4 */
-static struct omap_hwmod omap44xx_mmc4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
{ .irq = 96 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
- {
- .pa_start = 0x480d1000,
- .pa_end = 0x480d13ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> mmc4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mmc4_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mmc4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
- &omap44xx_l4_per__mmc4,
-};
-
static struct omap_hwmod omap44xx_mmc4_hwmod = {
.name = "mmc4",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mmc4_irqs,
-
.sdma_reqs = omap44xx_mmc4_sdma_reqs,
.main_clk = "mmc4_fck",
.prcm = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_mmc4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
};
/* mmc5 */
-static struct omap_hwmod omap44xx_mmc5_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
{ .irq = 59 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
- {
- .pa_start = 0x480d5000,
- .pa_end = 0x480d53ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> mmc5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mmc5_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_mmc5_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc5 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
- &omap44xx_l4_per__mmc5,
-};
-
static struct omap_hwmod omap44xx_mmc5_hwmod = {
.name = "mmc5",
.class = &omap44xx_mmc_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_mmc5_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
};
/*
{ .irq = -1 }
};
-/* mpu master ports */
-static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
- &omap44xx_mpu__l3_main_1,
- &omap44xx_mpu__l4_abe,
- &omap44xx_mpu__dmm,
-};
-
static struct omap_hwmod omap44xx_mpu_hwmod = {
.name = "mpu",
.class = &omap44xx_mpu_hwmod_class,
.context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
},
},
- .masters = omap44xx_mpu_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
};
/*
- * 'smartreflex' class
- * smartreflex module (monitor silicon performance and outputs a measure of
- * performance error)
+ * 'ocmc_ram' class
+ * top-level core on-chip ram
*/
-/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
- .sidle_shift = 24,
- .enwkup_shift = 26,
+static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
+ .name = "ocmc_ram",
};
-static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
- .sysc_offs = 0x0038,
- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
+/* ocmc_ram */
+static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
+ .name = "ocmc_ram",
+ .class = &omap44xx_ocmc_ram_hwmod_class,
+ .clkdm_name = "l3_2_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
+ },
+ },
};
-static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
- .name = "smartreflex",
- .sysc = &omap44xx_smartreflex_sysc,
- .rev = 2,
-};
+/*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
-/* smartreflex_core */
-static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
- .sensor_voltdm_name = "core",
+static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
+ .name = "ocp2scp",
};
-static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
-static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
- { .irq = 19 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
+/* ocp2scp_usb_phy */
+static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
+ { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
};
-static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
- {
- .pa_start = 0x4a0dd000,
- .pa_end = 0x4a0dd03f,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
+ .name = "ocp2scp_usb_phy",
+ .class = &omap44xx_ocp2scp_hwmod_class,
+ .clkdm_name = "l3_init_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
},
- { }
+ .opt_clks = ocp2scp_usb_phy_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
};
-/* l4_cfg -> smartreflex_core */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_smartreflex_core_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_smartreflex_core_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
+/*
+ * 'prcm' class
+ * power and reset manager (part of the prcm infrastructure) + clock manager 2
+ * + clock manager 1 (in always on power domain) + local prm in mpu
+ */
-/* smartreflex_core slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
- &omap44xx_l4_cfg__smartreflex_core,
+static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
+ .name = "prcm",
};
-static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
- .name = "smartreflex_core",
- .class = &omap44xx_smartreflex_hwmod_class,
- .clkdm_name = "l4_ao_clkdm",
- .mpu_irqs = omap44xx_smartreflex_core_irqs,
+/* prcm_mpu */
+static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
+ .name = "prcm_mpu",
+ .class = &omap44xx_prcm_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+};
- .main_clk = "smartreflex_core_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .slaves = omap44xx_smartreflex_core_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
- .dev_attr = &smartreflex_core_dev_attr,
+/* cm_core_aon */
+static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
+ .name = "cm_core_aon",
+ .class = &omap44xx_prcm_hwmod_class,
+ .clkdm_name = "cm_clkdm",
};
-/* smartreflex_iva */
-static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
- .sensor_voltdm_name = "iva",
+/* cm_core */
+static struct omap_hwmod omap44xx_cm_core_hwmod = {
+ .name = "cm_core",
+ .class = &omap44xx_prcm_hwmod_class,
+ .clkdm_name = "cm_clkdm",
};
-static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
-static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
- { .irq = 102 + OMAP44XX_IRQ_GIC_START },
+/* prm */
+static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
+ { .irq = 11 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
- {
- .pa_start = 0x4a0db000,
- .pa_end = 0x4a0db03f,
- .flags = ADDR_TYPE_RT
- },
- { }
+static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
+ { .name = "rst_global_warm_sw", .rst_shift = 0 },
+ { .name = "rst_global_cold_sw", .rst_shift = 1 },
};
-/* l4_cfg -> smartreflex_iva */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_smartreflex_iva_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_smartreflex_iva_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod omap44xx_prm_hwmod = {
+ .name = "prm",
+ .class = &omap44xx_prcm_hwmod_class,
+ .clkdm_name = "prm_clkdm",
+ .mpu_irqs = omap44xx_prm_irqs,
+ .rst_lines = omap44xx_prm_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
};
-/* smartreflex_iva slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
- &omap44xx_l4_cfg__smartreflex_iva,
+/*
+ * 'scrm' class
+ * system clock and reset manager
+ */
+
+static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
+ .name = "scrm",
};
-static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
- .name = "smartreflex_iva",
- .class = &omap44xx_smartreflex_hwmod_class,
- .clkdm_name = "l4_ao_clkdm",
- .mpu_irqs = omap44xx_smartreflex_iva_irqs,
- .main_clk = "smartreflex_iva_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .slaves = omap44xx_smartreflex_iva_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
- .dev_attr = &smartreflex_iva_dev_attr,
+/* scrm */
+static struct omap_hwmod omap44xx_scrm_hwmod = {
+ .name = "scrm",
+ .class = &omap44xx_scrm_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
};
-/* smartreflex_mpu */
-static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
- .sensor_voltdm_name = "mpu",
+/*
+ * 'sl2if' class
+ * shared level 2 memory interface
+ */
+
+static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
+ .name = "sl2if",
};
-static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
-static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
- { .irq = 18 + OMAP44XX_IRQ_GIC_START },
+/* sl2if */
+static struct omap_hwmod omap44xx_sl2if_hwmod = {
+ .name = "sl2if",
+ .class = &omap44xx_sl2if_hwmod_class,
+ .clkdm_name = "ivahd_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'slimbus' class
+ * bidirectional, multi-drop, multi-channel two-line serial interface between
+ * the device and external components
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
+ .name = "slimbus",
+ .sysc = &omap44xx_slimbus_sysc,
+};
+
+/* slimbus1 */
+static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
+ { .irq = 97 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
- {
- .pa_start = 0x4a0d9000,
- .pa_end = 0x4a0d903f,
- .flags = ADDR_TYPE_RT
+static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
+ { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
+ { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
+ { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
+ { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
+};
+
+static struct omap_hwmod omap44xx_slimbus1_hwmod = {
+ .name = "slimbus1",
+ .class = &omap44xx_slimbus_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .mpu_irqs = omap44xx_slimbus1_irqs,
+ .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
},
- { }
+ .opt_clks = slimbus1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
};
-/* l4_cfg -> smartreflex_mpu */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_smartreflex_mpu_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_smartreflex_mpu_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+/* slimbus2 */
+static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
+ { .irq = 98 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
-/* smartreflex_mpu slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
- &omap44xx_l4_cfg__smartreflex_mpu,
+static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
+ { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
+ { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
+ { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
+};
+
+static struct omap_hwmod omap44xx_slimbus2_hwmod = {
+ .name = "slimbus2",
+ .class = &omap44xx_slimbus_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_slimbus2_irqs,
+ .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = slimbus2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
+};
+
+/*
+ * 'smartreflex' class
+ * smartreflex module (monitor silicon performance and outputs a measure of
+ * performance error)
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
+ .sidle_shift = 24,
+ .enwkup_shift = 26,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
+ .sysc_offs = 0x0038,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
+};
+
+static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
+ .name = "smartreflex",
+ .sysc = &omap44xx_smartreflex_sysc,
+ .rev = 2,
+};
+
+/* smartreflex_core */
+static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
+ .sensor_voltdm_name = "core",
+};
+
+static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
+ { .irq = 19 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+ .name = "smartreflex_core",
+ .class = &omap44xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_ao_clkdm",
+ .mpu_irqs = omap44xx_smartreflex_core_irqs,
+
+ .main_clk = "smartreflex_core_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &smartreflex_core_dev_attr,
+};
+
+/* smartreflex_iva */
+static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
+ .sensor_voltdm_name = "iva",
+};
+
+static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
+ { .irq = 102 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+ .name = "smartreflex_iva",
+ .class = &omap44xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_ao_clkdm",
+ .mpu_irqs = omap44xx_smartreflex_iva_irqs,
+ .main_clk = "smartreflex_iva_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &smartreflex_iva_dev_attr,
+};
+
+/* smartreflex_mpu */
+static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
+ .sensor_voltdm_name = "mpu",
+};
+
+static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
+ { .irq = 18 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_smartreflex_mpu_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
.dev_attr = &smartreflex_mpu_dev_attr,
};
};
/* spinlock */
-static struct omap_hwmod omap44xx_spinlock_hwmod;
-static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
- {
- .pa_start = 0x4a0f6000,
- .pa_end = 0x4a0f6fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_cfg -> spinlock */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_spinlock_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_spinlock_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* spinlock slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
- &omap44xx_l4_cfg__spinlock,
-};
-
static struct omap_hwmod omap44xx_spinlock_hwmod = {
.name = "spinlock",
.class = &omap44xx_spinlock_hwmod_class,
.context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
},
},
- .slaves = omap44xx_spinlock_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
};
/*
};
/* timer1 */
-static struct omap_hwmod omap44xx_timer1_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
- {
- .pa_start = 0x4a318000,
- .pa_end = 0x4a31807f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_timer1_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_timer1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
- &omap44xx_l4_wkup__timer1,
-};
-
static struct omap_hwmod omap44xx_timer1_hwmod = {
.name = "timer1",
.class = &omap44xx_timer_1ms_hwmod_class,
},
},
.dev_attr = &capability_alwon_dev_attr,
- .slaves = omap44xx_timer1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
};
/* timer2 */
-static struct omap_hwmod omap44xx_timer2_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
{ .irq = 38 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
- {
- .pa_start = 0x48032000,
- .pa_end = 0x4803207f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer2_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_timer2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
- &omap44xx_l4_per__timer2,
-};
-
static struct omap_hwmod omap44xx_timer2_hwmod = {
.name = "timer2",
.class = &omap44xx_timer_1ms_hwmod_class,
},
},
.dev_attr = &capability_alwon_dev_attr,
- .slaves = omap44xx_timer2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
};
/* timer3 */
-static struct omap_hwmod omap44xx_timer3_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
{ .irq = 39 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
- {
- .pa_start = 0x48034000,
- .pa_end = 0x4803407f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> timer3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer3_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_timer3_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
- &omap44xx_l4_per__timer3,
-};
-
static struct omap_hwmod omap44xx_timer3_hwmod = {
.name = "timer3",
.class = &omap44xx_timer_hwmod_class,
},
},
.dev_attr = &capability_alwon_dev_attr,
- .slaves = omap44xx_timer3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
};
/* timer4 */
-static struct omap_hwmod omap44xx_timer4_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
{ .irq = 40 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
- {
- .pa_start = 0x48036000,
- .pa_end = 0x4803607f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> timer4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer4_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_timer4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
- &omap44xx_l4_per__timer4,
-};
-
-static struct omap_hwmod omap44xx_timer4_hwmod = {
- .name = "timer4",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_timer4_irqs,
- .main_clk = "timer4_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
+static struct omap_hwmod omap44xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &omap44xx_timer_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
+ .mpu_irqs = omap44xx_timer4_irqs,
+ .main_clk = "timer4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
},
.dev_attr = &capability_alwon_dev_attr,
- .slaves = omap44xx_timer4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
};
/* timer5 */
-static struct omap_hwmod omap44xx_timer5_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
{ .irq = 41 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
- {
- .pa_start = 0x40138000,
- .pa_end = 0x4013807f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> timer5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer5_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_timer5_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
- {
- .pa_start = 0x49038000,
- .pa_end = 0x4903807f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> timer5 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer5_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_timer5_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* timer5 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
- &omap44xx_l4_abe__timer5,
- &omap44xx_l4_abe__timer5_dma,
-};
-
static struct omap_hwmod omap44xx_timer5_hwmod = {
.name = "timer5",
.class = &omap44xx_timer_hwmod_class,
},
},
.dev_attr = &capability_alwon_dev_attr,
- .slaves = omap44xx_timer5_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
};
/* timer6 */
-static struct omap_hwmod omap44xx_timer6_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
{ .irq = 42 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
- {
- .pa_start = 0x4013a000,
- .pa_end = 0x4013a07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> timer6 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer6_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_timer6_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
- {
- .pa_start = 0x4903a000,
- .pa_end = 0x4903a07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> timer6 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer6_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_timer6_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* timer6 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
- &omap44xx_l4_abe__timer6,
- &omap44xx_l4_abe__timer6_dma,
-};
-
static struct omap_hwmod omap44xx_timer6_hwmod = {
.name = "timer6",
.class = &omap44xx_timer_hwmod_class,
},
},
.dev_attr = &capability_alwon_dev_attr,
- .slaves = omap44xx_timer6_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
};
/* timer7 */
-static struct omap_hwmod omap44xx_timer7_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
{ .irq = 43 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
- {
- .pa_start = 0x4013c000,
- .pa_end = 0x4013c07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> timer7 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer7_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_timer7_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
- {
- .pa_start = 0x4903c000,
- .pa_end = 0x4903c07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> timer7 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer7_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_timer7_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* timer7 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
- &omap44xx_l4_abe__timer7,
- &omap44xx_l4_abe__timer7_dma,
-};
-
static struct omap_hwmod omap44xx_timer7_hwmod = {
.name = "timer7",
.class = &omap44xx_timer_hwmod_class,
},
},
.dev_attr = &capability_alwon_dev_attr,
- .slaves = omap44xx_timer7_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
};
/* timer8 */
-static struct omap_hwmod omap44xx_timer8_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
{ .irq = 44 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
- {
- .pa_start = 0x4013e000,
- .pa_end = 0x4013e07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> timer8 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer8_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_timer8_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
- {
- .pa_start = 0x4903e000,
- .pa_end = 0x4903e07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> timer8 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer8_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_timer8_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* timer8 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
- &omap44xx_l4_abe__timer8,
- &omap44xx_l4_abe__timer8_dma,
-};
-
static struct omap_hwmod omap44xx_timer8_hwmod = {
.name = "timer8",
.class = &omap44xx_timer_hwmod_class,
},
},
.dev_attr = &capability_pwm_dev_attr,
- .slaves = omap44xx_timer8_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
};
/* timer9 */
-static struct omap_hwmod omap44xx_timer9_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
{ .irq = 45 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
- {
- .pa_start = 0x4803e000,
- .pa_end = 0x4803e07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> timer9 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer9_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_timer9_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer9 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
- &omap44xx_l4_per__timer9,
-};
-
static struct omap_hwmod omap44xx_timer9_hwmod = {
.name = "timer9",
.class = &omap44xx_timer_hwmod_class,
},
},
.dev_attr = &capability_pwm_dev_attr,
- .slaves = omap44xx_timer9_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
};
/* timer10 */
-static struct omap_hwmod omap44xx_timer10_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
{ .irq = 46 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
- {
- .pa_start = 0x48086000,
- .pa_end = 0x4808607f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> timer10 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer10_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_timer10_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer10 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
- &omap44xx_l4_per__timer10,
-};
-
static struct omap_hwmod omap44xx_timer10_hwmod = {
.name = "timer10",
.class = &omap44xx_timer_1ms_hwmod_class,
},
},
.dev_attr = &capability_pwm_dev_attr,
- .slaves = omap44xx_timer10_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
};
/* timer11 */
-static struct omap_hwmod omap44xx_timer11_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
{ .irq = 47 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
- {
- .pa_start = 0x48088000,
- .pa_end = 0x4808807f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> timer11 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer11_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_timer11_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer11 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
- &omap44xx_l4_per__timer11,
-};
-
static struct omap_hwmod omap44xx_timer11_hwmod = {
.name = "timer11",
.class = &omap44xx_timer_hwmod_class,
},
},
.dev_attr = &capability_pwm_dev_attr,
- .slaves = omap44xx_timer11_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
};
/*
};
/* uart1 */
-static struct omap_hwmod omap44xx_uart1_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
{ .irq = 72 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
- {
- .pa_start = 0x4806a000,
- .pa_end = 0x4806a0ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> uart1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_uart1_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_uart1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* uart1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
- &omap44xx_l4_per__uart1,
-};
-
static struct omap_hwmod omap44xx_uart1_hwmod = {
.name = "uart1",
.class = &omap44xx_uart_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_uart1_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
};
/* uart2 */
-static struct omap_hwmod omap44xx_uart2_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
{ .irq = 73 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
- {
- .pa_start = 0x4806c000,
- .pa_end = 0x4806c0ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> uart2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_uart2_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_uart2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* uart2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
- &omap44xx_l4_per__uart2,
-};
-
static struct omap_hwmod omap44xx_uart2_hwmod = {
.name = "uart2",
.class = &omap44xx_uart_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_uart2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
};
/* uart3 */
-static struct omap_hwmod omap44xx_uart3_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
{ .irq = 74 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
- {
- .pa_start = 0x48020000,
- .pa_end = 0x480200ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> uart3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_uart3_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_uart3_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* uart3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
- &omap44xx_l4_per__uart3,
-};
-
static struct omap_hwmod omap44xx_uart3_hwmod = {
.name = "uart3",
.class = &omap44xx_uart_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_uart3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
};
/* uart4 */
-static struct omap_hwmod omap44xx_uart4_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
{ .irq = 70 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
{ .dma_req = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
- {
- .pa_start = 0x4806e000,
- .pa_end = 0x4806e0ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_per -> uart4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_uart4_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_uart4_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* uart4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
- &omap44xx_l4_per__uart4,
-};
-
static struct omap_hwmod omap44xx_uart4_hwmod = {
.name = "uart4",
.class = &omap44xx_uart_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_uart4_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
+};
+
+/*
+ * 'usb_host_fs' class
+ * full-speed usb host controller
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
+ .midle_shift = 4,
+ .sidle_shift = 2,
+ .srst_shift = 1,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0210,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
+};
+
+static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
+ .name = "usb_host_fs",
+ .sysc = &omap44xx_usb_host_fs_sysc,
+};
+
+/* usb_host_fs */
+static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
+ { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
+ { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
+ .name = "usb_host_fs",
+ .class = &omap44xx_usb_host_fs_hwmod_class,
+ .clkdm_name = "l3_init_clkdm",
+ .mpu_irqs = omap44xx_usb_host_fs_irqs,
+ .main_clk = "usb_host_fs_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'usb_host_hs' class
+ * high-speed multi-port usb host controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
+ .name = "usb_host_hs",
+ .sysc = &omap44xx_usb_host_hs_sysc,
+};
+
+/* usb_host_hs */
+static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
+ { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
+ { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
+ .name = "usb_host_hs",
+ .class = &omap44xx_usb_host_hs_hwmod_class,
+ .clkdm_name = "l3_init_clkdm",
+ .main_clk = "usb_host_hs_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .mpu_irqs = omap44xx_usb_host_hs_irqs,
+
+ /*
+ * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
+ * id: i660
+ *
+ * Description:
+ * In the following configuration :
+ * - USBHOST module is set to smart-idle mode
+ * - PRCM asserts idle_req to the USBHOST module ( This typically
+ * happens when the system is going to a low power mode : all ports
+ * have been suspended, the master part of the USBHOST module has
+ * entered the standby state, and SW has cut the functional clocks)
+ * - an USBHOST interrupt occurs before the module is able to answer
+ * idle_ack, typically a remote wakeup IRQ.
+ * Then the USB HOST module will enter a deadlock situation where it
+ * is no more accessible nor functional.
+ *
+ * Workaround:
+ * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
+ */
+
+ /*
+ * Errata: USB host EHCI may stall when entering smart-standby mode
+ * Id: i571
+ *
+ * Description:
+ * When the USBHOST module is set to smart-standby mode, and when it is
+ * ready to enter the standby state (i.e. all ports are suspended and
+ * all attached devices are in suspend mode), then it can wrongly assert
+ * the Mstandby signal too early while there are still some residual OCP
+ * transactions ongoing. If this condition occurs, the internal state
+ * machine may go to an undefined state and the USB link may be stuck
+ * upon the next resume.
+ *
+ * Workaround:
+ * Don't use smart standby; use only force standby,
+ * hence HWMOD_SWSUP_MSTANDBY
+ */
+
+ /*
+ * During system boot; If the hwmod framework resets the module
+ * the module will have smart idle settings; which can lead to deadlock
+ * (above Errata Id:i660); so, dont reset the module during boot;
+ * Use HWMOD_INIT_NO_RESET.
+ */
+
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ HWMOD_INIT_NO_RESET,
};
/*
{ .irq = -1 }
};
-/* usb_otg_hs master ports */
-static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
- &omap44xx_usb_otg_hs__l3_main_2,
-};
-
-static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
- {
- .pa_start = 0x4a0ab000,
- .pa_end = 0x4a0ab003,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_cfg -> usb_otg_hs */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_otg_hs_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_usb_otg_hs_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* usb_otg_hs slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
- &omap44xx_l4_cfg__usb_otg_hs,
-};
-
static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
};
},
.opt_clks = usb_otg_hs_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
- .slaves = omap44xx_usb_otg_hs_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
- .masters = omap44xx_usb_otg_hs_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
};
/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
+ * 'usb_tll_hs' class
+ * usb_tll_hs module is the adapter on the usb_host_hs ports
*/
-static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
+static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
-static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &omap44xx_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable,
+static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
+ .name = "usb_tll_hs",
+ .sysc = &omap44xx_usb_tll_hs_sysc,
};
-/* wd_timer2 */
-static struct omap_hwmod omap44xx_wd_timer2_hwmod;
-static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
- { .irq = 80 + OMAP44XX_IRQ_GIC_START },
+static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
+ { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
- {
- .pa_start = 0x4a314000,
- .pa_end = 0x4a31407f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_wd_timer2_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_wd_timer2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
+ .name = "usb_tll_hs",
+ .class = &omap44xx_usb_tll_hs_hwmod_class,
+ .clkdm_name = "l3_init_clkdm",
+ .mpu_irqs = omap44xx_usb_tll_hs_irqs,
+ .main_clk = "usb_tll_hs_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
};
-/* wd_timer2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
- &omap44xx_l4_wkup__wd_timer2,
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+ .sysc = &omap44xx_wd_timer_sysc,
+ .pre_shutdown = &omap2_wd_timer_disable,
+ .reset = &omap2_wd_timer_reset,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
+ { .irq = 80 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_wd_timer2_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
};
/* wd_timer3 */
-static struct omap_hwmod omap44xx_wd_timer3_hwmod;
static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
-static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
- {
- .pa_start = 0x40130000,
- .pa_end = 0x4013007f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> wd_timer3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_wd_timer3_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_wd_timer3_addrs,
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
- {
- .pa_start = 0x49030000,
- .pa_end = 0x4903007f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_abe -> wd_timer3 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_wd_timer3_hwmod,
- .clk = "ocp_abe_iclk",
- .addr = omap44xx_wd_timer3_dma_addrs,
- .user = OCP_USER_SDMA,
-};
-
-/* wd_timer3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
- &omap44xx_l4_abe__wd_timer3,
- &omap44xx_l4_abe__wd_timer3_dma,
-};
-
static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.name = "wd_timer3",
.class = &omap44xx_wd_timer_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = omap44xx_wd_timer3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
};
+
/*
- * 'usb_host_hs' class
- * high-speed multi-port usb host controller
+ * interfaces
*/
-static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
- .master = &omap44xx_usb_host_hs_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
- .name = "usb_host_hs",
- .sysc = &omap44xx_usb_host_hs_sysc,
-};
-static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
- &omap44xx_usb_host_hs__l3_main_2,
-};
-
-static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
+static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
{
- .name = "uhh",
- .pa_start = 0x4a064000,
- .pa_end = 0x4a0647ff,
+ .pa_start = 0x4a204000,
+ .pa_end = 0x4a2040ff,
.flags = ADDR_TYPE_RT
},
- {
- .name = "ohci",
- .pa_start = 0x4a064800,
- .pa_end = 0x4a064bff,
- },
- {
- .name = "ehci",
- .pa_start = 0x4a064c00,
- .pa_end = 0x4a064fff,
- },
- {}
+ { }
};
-static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
- { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
- { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
+/* c2c -> c2c_target_fw */
+static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
+ .master = &omap44xx_c2c_hwmod,
+ .slave = &omap44xx_c2c_target_fw_hwmod,
+ .clk = "div_core_ck",
+ .addr = omap44xx_c2c_target_fw_addrs,
+ .user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
+/* l4_cfg -> c2c_target_fw */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
.master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_host_hs_hwmod,
+ .slave = &omap44xx_c2c_target_fw_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_usb_host_hs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
- &omap44xx_l4_cfg__usb_host_hs,
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
+ .master = &omap44xx_l3_main_1_hwmod,
+ .slave = &omap44xx_dmm_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_SDMA,
};
-static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
- .name = "usb_host_hs",
- .class = &omap44xx_usb_host_hs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .main_clk = "usb_host_hs_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
+static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
+ {
+ .pa_start = 0x4e000000,
+ .pa_end = 0x4e0007ff,
+ .flags = ADDR_TYPE_RT
},
- .mpu_irqs = omap44xx_usb_host_hs_irqs,
- .slaves = omap44xx_usb_host_hs_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
- .masters = omap44xx_usb_host_hs_masters,
- .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
-
- /*
- * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
- * id: i660
- *
- * Description:
- * In the following configuration :
- * - USBHOST module is set to smart-idle mode
- * - PRCM asserts idle_req to the USBHOST module ( This typically
- * happens when the system is going to a low power mode : all ports
- * have been suspended, the master part of the USBHOST module has
- * entered the standby state, and SW has cut the functional clocks)
- * - an USBHOST interrupt occurs before the module is able to answer
- * idle_ack, typically a remote wakeup IRQ.
- * Then the USB HOST module will enter a deadlock situation where it
- * is no more accessible nor functional.
- *
- * Workaround:
- * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
- */
-
- /*
- * Errata: USB host EHCI may stall when entering smart-standby mode
- * Id: i571
- *
- * Description:
- * When the USBHOST module is set to smart-standby mode, and when it is
- * ready to enter the standby state (i.e. all ports are suspended and
- * all attached devices are in suspend mode), then it can wrongly assert
- * the Mstandby signal too early while there are still some residual OCP
- * transactions ongoing. If this condition occurs, the internal state
- * machine may go to an undefined state and the USB link may be stuck
- * upon the next resume.
- *
- * Workaround:
- * Don't use smart standby; use only force standby,
- * hence HWMOD_SWSUP_MSTANDBY
- */
-
- /*
- * During system boot; If the hwmod framework resets the module
- * the module will have smart idle settings; which can lead to deadlock
- * (above Errata Id:i660); so, dont reset the module during boot;
- * Use HWMOD_INIT_NO_RESET.
- */
-
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
- HWMOD_INIT_NO_RESET,
+ { }
};
-/*
- * 'usb_tll_hs' class
- * usb_tll_hs module is the adapter on the usb_host_hs ports
- */
-static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
+/* mpu -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
+ .master = &omap44xx_mpu_hwmod,
+ .slave = &omap44xx_dmm_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dmm_addrs,
+ .user = OCP_USER_MPU,
};
-static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
- .name = "usb_tll_hs",
- .sysc = &omap44xx_usb_tll_hs_sysc,
+/* c2c -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
+ .master = &omap44xx_c2c_hwmod,
+ .slave = &omap44xx_emif_fw_hwmod,
+ .clk = "div_core_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
- { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
+/* dmm -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
+ .master = &omap44xx_dmm_hwmod,
+ .slave = &omap44xx_emif_fw_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
+static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
{
- .name = "tll",
- .pa_start = 0x4a062000,
- .pa_end = 0x4a063fff,
+ .pa_start = 0x4a20c000,
+ .pa_end = 0x4a20c0ff,
.flags = ADDR_TYPE_RT
},
- {}
+ { }
};
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
+/* l4_cfg -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
.master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_tll_hs_hwmod,
+ .slave = &omap44xx_emif_fw_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_usb_tll_hs_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .addr = omap44xx_emif_fw_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* iva -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
+ .master = &omap44xx_iva_hwmod,
+ .slave = &omap44xx_l3_instr_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
+ .master = &omap44xx_l3_main_3_hwmod,
+ .slave = &omap44xx_l3_instr_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ocp_wp_noc -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
+ .master = &omap44xx_ocp_wp_noc_hwmod,
+ .slave = &omap44xx_l3_instr_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dsp -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
+ .master = &omap44xx_dsp_hwmod,
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
+ .master = &omap44xx_dss_hwmod,
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l4_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc1 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
+ .master = &omap44xx_mmc1_hwmod,
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
+ .master = &omap44xx_mmc2_hwmod,
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
+ {
+ .pa_start = 0x44000000,
+ .pa_end = 0x44000fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+ .master = &omap44xx_mpu_hwmod,
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_l3_main_1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* c2c_target_fw -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
+ .master = &omap44xx_c2c_target_fw_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* debugss -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
+ .master = &omap44xx_debugss_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "dbgclk_mux_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
+ .master = &omap44xx_dma_system_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* fdif -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
+ .master = &omap44xx_fdif_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpu -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
+ .master = &omap44xx_gpu_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* hsi -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
+ .master = &omap44xx_hsi_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ipu -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
+ .master = &omap44xx_ipu_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iss -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
+ .master = &omap44xx_iss_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iva -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
+ .master = &omap44xx_iva_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
+ {
+ .pa_start = 0x44800000,
+ .pa_end = 0x44801fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
+ .master = &omap44xx_l3_main_1_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_l3_main_2_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l4_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_host_fs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
+ .master = &omap44xx_usb_host_fs_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_host_hs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
+ .master = &omap44xx_usb_host_hs_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_otg_hs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
+ .master = &omap44xx_usb_otg_hs_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
+ {
+ .pa_start = 0x45000000,
+ .pa_end = 0x45000fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
+ .master = &omap44xx_l3_main_1_hwmod,
+ .slave = &omap44xx_l3_main_3_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_l3_main_3_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_l3_main_3_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_l3_main_3_hwmod,
+ .clk = "l4_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* aess -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
+ .master = &omap44xx_aess_hwmod,
+ .slave = &omap44xx_l4_abe_hwmod,
+ .clk = "ocp_abe_iclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dsp -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
+ .master = &omap44xx_dsp_hwmod,
+ .slave = &omap44xx_l4_abe_hwmod,
+ .clk = "ocp_abe_iclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
+ .master = &omap44xx_l3_main_1_hwmod,
+ .slave = &omap44xx_l4_abe_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
+ .master = &omap44xx_mpu_hwmod,
+ .slave = &omap44xx_l4_abe_hwmod,
+ .clk = "ocp_abe_iclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
+ .master = &omap44xx_l3_main_1_hwmod,
+ .slave = &omap44xx_l4_cfg_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_l4_per_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l4_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_l4_wkup_hwmod,
+ .clk = "l4_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
+ .master = &omap44xx_mpu_hwmod,
+ .slave = &omap44xx_mpu_private_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
+ {
+ .pa_start = 0x4a102000,
+ .pa_end = 0x4a10207f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> ocp_wp_noc */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_ocp_wp_noc_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_ocp_wp_noc_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
+ {
+ .pa_start = 0x401f1000,
+ .pa_end = 0x401f13ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> aess */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_aess_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_aess_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
+ {
+ .pa_start = 0x490f1000,
+ .pa_end = 0x490f13ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> aess (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_aess_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_aess_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> c2c */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_c2c_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
+ {
+ .pa_start = 0x4a304000,
+ .pa_end = 0x4a30401f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_counter_32k_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_counter_32k_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
+ {
+ .pa_start = 0x4a002000,
+ .pa_end = 0x4a0027ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> ctrl_module_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_ctrl_module_core_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_ctrl_module_core_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
+ {
+ .pa_start = 0x4a100000,
+ .pa_end = 0x4a1007ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> ctrl_module_pad_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_ctrl_module_pad_core_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_ctrl_module_pad_core_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
+ {
+ .pa_start = 0x4a30c000,
+ .pa_end = 0x4a30c7ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> ctrl_module_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_ctrl_module_wkup_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_ctrl_module_wkup_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
+ {
+ .pa_start = 0x4a31e000,
+ .pa_end = 0x4a31e7ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> ctrl_module_pad_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_ctrl_module_pad_wkup_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
+ {
+ .pa_start = 0x54160000,
+ .pa_end = 0x54167fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_instr -> debugss */
+static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
+ .master = &omap44xx_l3_instr_hwmod,
+ .slave = &omap44xx_debugss_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_debugss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
+ {
+ .pa_start = 0x4a056000,
+ .pa_end = 0x4a056fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_dma_system_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dma_system_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x4012e000,
+ .pa_end = 0x4012e07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> dmic */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_dmic_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_dmic_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
+ {
+ .name = "dma",
+ .pa_start = 0x4902e000,
+ .pa_end = 0x4902e07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> dmic (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_dmic_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_dmic_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+/* dsp -> iva */
+static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
+ .master = &omap44xx_dsp_hwmod,
+ .slave = &omap44xx_iva_hwmod,
+ .clk = "dpll_iva_m5x2_ck",
+ .user = OCP_USER_DSP,
+};
+
+/* dsp -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
+ .master = &omap44xx_dsp_hwmod,
+ .slave = &omap44xx_sl2if_hwmod,
+ .clk = "dpll_iva_m5x2_ck",
+ .user = OCP_USER_DSP,
+};
+
+/* l4_cfg -> dsp */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_dsp_hwmod,
+ .clk = "l4_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
+ {
+ .pa_start = 0x58000000,
+ .pa_end = 0x5800007f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_hwmod,
+ .clk = "dss_fck",
+ .addr = omap44xx_dss_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
+ {
+ .pa_start = 0x48040000,
+ .pa_end = 0x4804007f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+ {
+ .pa_start = 0x58001000,
+ .pa_end = 0x58001fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_dispc_hwmod,
+ .clk = "dss_fck",
+ .addr = omap44xx_dss_dispc_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
+ {
+ .pa_start = 0x48041000,
+ .pa_end = 0x48041fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_dispc_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_dispc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
+ {
+ .pa_start = 0x58004000,
+ .pa_end = 0x580041ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_dsi1_hwmod,
+ .clk = "dss_fck",
+ .addr = omap44xx_dss_dsi1_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
+ {
+ .pa_start = 0x48044000,
+ .pa_end = 0x480441ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_dsi1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_dsi1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
+ {
+ .pa_start = 0x58005000,
+ .pa_end = 0x580051ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_dsi2_hwmod,
+ .clk = "dss_fck",
+ .addr = omap44xx_dss_dsi2_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
+ {
+ .pa_start = 0x48045000,
+ .pa_end = 0x480451ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_dsi2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_dsi2_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
+ {
+ .pa_start = 0x58006000,
+ .pa_end = 0x58006fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_hdmi_hwmod,
+ .clk = "dss_fck",
+ .addr = omap44xx_dss_hdmi_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
+ {
+ .pa_start = 0x48046000,
+ .pa_end = 0x48046fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_hdmi_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_hdmi_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
+ {
+ .pa_start = 0x58002000,
+ .pa_end = 0x580020ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_rfbi_hwmod,
+ .clk = "dss_fck",
+ .addr = omap44xx_dss_rfbi_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
+ {
+ .pa_start = 0x48042000,
+ .pa_end = 0x480420ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_rfbi_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_rfbi_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
+ {
+ .pa_start = 0x58003000,
+ .pa_end = 0x580030ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_venc_hwmod,
+ .clk = "dss_fck",
+ .addr = omap44xx_dss_venc_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
+ {
+ .pa_start = 0x48043000,
+ .pa_end = 0x480430ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_venc_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_venc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
+ {
+ .pa_start = 0x48078000,
+ .pa_end = 0x48078fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> elm */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_elm_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_elm_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
+ {
+ .pa_start = 0x4c000000,
+ .pa_end = 0x4c0000ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* emif_fw -> emif1 */
+static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
+ .master = &omap44xx_emif_fw_hwmod,
+ .slave = &omap44xx_emif1_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_emif1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
+ {
+ .pa_start = 0x4d000000,
+ .pa_end = 0x4d0000ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* emif_fw -> emif2 */
+static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
+ .master = &omap44xx_emif_fw_hwmod,
+ .slave = &omap44xx_emif2_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_emif2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
+ {
+ .pa_start = 0x4a10a000,
+ .pa_end = 0x4a10a1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> fdif */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_fdif_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_fdif_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
+ {
+ .pa_start = 0x4a310000,
+ .pa_end = 0x4a3101ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_gpio1_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_gpio1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
+ {
+ .pa_start = 0x48055000,
+ .pa_end = 0x480551ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_gpio2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_gpio2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
+ {
+ .pa_start = 0x48057000,
+ .pa_end = 0x480571ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_gpio3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_gpio3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
+ {
+ .pa_start = 0x48059000,
+ .pa_end = 0x480591ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_gpio4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_gpio4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
+ {
+ .pa_start = 0x4805b000,
+ .pa_end = 0x4805b1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_gpio5_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_gpio5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
+ {
+ .pa_start = 0x4805d000,
+ .pa_end = 0x4805d1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_gpio6_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_gpio6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
+ {
+ .pa_start = 0x50000000,
+ .pa_end = 0x500003ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> gpmc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_gpmc_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_gpmc_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
+ {
+ .pa_start = 0x56000000,
+ .pa_end = 0x5600ffff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> gpu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_gpu_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_gpu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
+ {
+ .pa_start = 0x480b2000,
+ .pa_end = 0x480b201f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> hdq1w */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_hdq1w_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_hdq1w_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
+ {
+ .pa_start = 0x4a058000,
+ .pa_end = 0x4a05bfff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> hsi */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_hsi_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_hsi_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
+ {
+ .pa_start = 0x48070000,
+ .pa_end = 0x480700ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_i2c1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
+ {
+ .pa_start = 0x48072000,
+ .pa_end = 0x480720ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_i2c2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
+ {
+ .pa_start = 0x48060000,
+ .pa_end = 0x480600ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_i2c3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
+ {
+ .pa_start = 0x48350000,
+ .pa_end = 0x483500ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_i2c4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_i2c4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> ipu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_ipu_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
+ {
+ .pa_start = 0x52000000,
+ .pa_end = 0x520000ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> iss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_iss_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_iss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iva -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
+ .master = &omap44xx_iva_hwmod,
+ .slave = &omap44xx_sl2if_hwmod,
+ .clk = "dpll_iva_m5x2_ck",
+ .user = OCP_USER_IVA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
+ {
+ .pa_start = 0x5a000000,
+ .pa_end = 0x5a07ffff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_2 -> iva */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_iva_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_iva_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
+ {
+ .pa_start = 0x4a31c000,
+ .pa_end = 0x4a31c07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> kbd */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_kbd_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_kbd_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x4a0f4000,
+ .pa_end = 0x4a0f41ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> mailbox */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_mailbox_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mailbox_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
+ {
+ .pa_start = 0x40128000,
+ .pa_end = 0x401283ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> mcasp */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_mcasp_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcasp_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
+ {
+ .pa_start = 0x49028000,
+ .pa_end = 0x490283ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> mcasp (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_mcasp_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcasp_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x40122000,
+ .pa_end = 0x401220ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_mcbsp1_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
+ {
+ .name = "dma",
+ .pa_start = 0x49022000,
+ .pa_end = 0x490220ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> mcbsp1 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_mcbsp1_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp1_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x40124000,
+ .pa_end = 0x401240ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_mcbsp2_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp2_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
+ {
+ .name = "dma",
+ .pa_start = 0x49024000,
+ .pa_end = 0x490240ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> mcbsp2 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_mcbsp2_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp2_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x40126000,
+ .pa_end = 0x401260ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_mcbsp3_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp3_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
+ {
+ .name = "dma",
+ .pa_start = 0x49026000,
+ .pa_end = 0x490260ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> mcbsp3 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_mcbsp3_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcbsp3_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
+ {
+ .pa_start = 0x48096000,
+ .pa_end = 0x480960ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mcbsp4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcbsp4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
+ {
+ .pa_start = 0x40132000,
+ .pa_end = 0x4013207f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> mcpdm */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_mcpdm_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcpdm_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
+ {
+ .pa_start = 0x49032000,
+ .pa_end = 0x4903207f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> mcpdm (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_mcpdm_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_mcpdm_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+ {
+ .pa_start = 0x48098000,
+ .pa_end = 0x480981ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mcspi1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+ {
+ .pa_start = 0x4809a000,
+ .pa_end = 0x4809a1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mcspi2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+ {
+ .pa_start = 0x480b8000,
+ .pa_end = 0x480b81ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mcspi3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+ {
+ .pa_start = 0x480ba000,
+ .pa_end = 0x480ba1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mcspi4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
+ {
+ .pa_start = 0x4809c000,
+ .pa_end = 0x4809c3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> mmc1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mmc1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmc1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
+ {
+ .pa_start = 0x480b4000,
+ .pa_end = 0x480b43ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> mmc2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mmc2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmc2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
+ {
+ .pa_start = 0x480ad000,
+ .pa_end = 0x480ad3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> mmc3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mmc3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmc3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
+ {
+ .pa_start = 0x480d1000,
+ .pa_end = 0x480d13ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> mmc4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mmc4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmc4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
+ {
+ .pa_start = 0x480d5000,
+ .pa_end = 0x480d53ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> mmc5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mmc5_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmc5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> ocmc_ram */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_ocmc_ram_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> ocp2scp_usb_phy */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
+ .clk = "l4_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
+ {
+ .pa_start = 0x48243000,
+ .pa_end = 0x48243fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* mpu_private -> prcm_mpu */
+static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
+ .master = &omap44xx_mpu_private_hwmod,
+ .slave = &omap44xx_prcm_mpu_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_prcm_mpu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
+ {
+ .pa_start = 0x4a004000,
+ .pa_end = 0x4a004fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> cm_core_aon */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_cm_core_aon_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_cm_core_aon_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
+ {
+ .pa_start = 0x4a008000,
+ .pa_end = 0x4a009fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> cm_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_cm_core_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_cm_core_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
+ {
+ .pa_start = 0x4a306000,
+ .pa_end = 0x4a307fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> prm */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_prm_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_prm_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
+ {
+ .pa_start = 0x4a30a000,
+ .pa_end = 0x4a30a7ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> scrm */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_scrm_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_scrm_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_sl2if_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
+ {
+ .pa_start = 0x4012c000,
+ .pa_end = 0x4012c3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> slimbus1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_slimbus1_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_slimbus1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
+ {
+ .pa_start = 0x4902c000,
+ .pa_end = 0x4902c3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> slimbus1 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_slimbus1_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_slimbus1_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
+ {
+ .pa_start = 0x48076000,
+ .pa_end = 0x480763ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> slimbus2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_slimbus2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_slimbus2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+ {
+ .pa_start = 0x4a0dd000,
+ .pa_end = 0x4a0dd03f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_smartreflex_core_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_smartreflex_core_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
+ {
+ .pa_start = 0x4a0db000,
+ .pa_end = 0x4a0db03f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_iva */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_smartreflex_iva_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_smartreflex_iva_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
+ {
+ .pa_start = 0x4a0d9000,
+ .pa_end = 0x4a0d903f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_smartreflex_mpu_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_smartreflex_mpu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
+ {
+ .pa_start = 0x4a0f6000,
+ .pa_end = 0x4a0f6fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> spinlock */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_spinlock_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_spinlock_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+ {
+ .pa_start = 0x4a318000,
+ .pa_end = 0x4a31807f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_timer1_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_timer1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+ {
+ .pa_start = 0x48032000,
+ .pa_end = 0x4803207f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
+ {
+ .pa_start = 0x48034000,
+ .pa_end = 0x4803407f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
+ {
+ .pa_start = 0x48036000,
+ .pa_end = 0x4803607f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
+ {
+ .pa_start = 0x40138000,
+ .pa_end = 0x4013807f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer5_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer5_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
+ {
+ .pa_start = 0x49038000,
+ .pa_end = 0x4903807f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> timer5 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer5_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer5_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
+ {
+ .pa_start = 0x4013a000,
+ .pa_end = 0x4013a07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer6_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer6_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
+ {
+ .pa_start = 0x4903a000,
+ .pa_end = 0x4903a07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> timer6 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer6_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer6_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
+ {
+ .pa_start = 0x4013c000,
+ .pa_end = 0x4013c07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer7_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer7_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
+ {
+ .pa_start = 0x4903c000,
+ .pa_end = 0x4903c07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> timer7 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer7_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer7_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
+ {
+ .pa_start = 0x4013e000,
+ .pa_end = 0x4013e07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer8_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer8_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
+ {
+ .pa_start = 0x4903e000,
+ .pa_end = 0x4903e07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> timer8 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer8_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer8_dma_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
+ {
+ .pa_start = 0x4803e000,
+ .pa_end = 0x4803e07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer9_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
+ {
+ .pa_start = 0x48086000,
+ .pa_end = 0x4808607f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer10_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
+ {
+ .pa_start = 0x48088000,
+ .pa_end = 0x4808807f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer11_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer11_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
+ {
+ .pa_start = 0x4806a000,
+ .pa_end = 0x4806a0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_uart1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_uart1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
+ {
+ .pa_start = 0x4806c000,
+ .pa_end = 0x4806c0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_uart2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_uart2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
+ {
+ .pa_start = 0x48020000,
+ .pa_end = 0x480200ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_uart3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_uart3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
+ {
+ .pa_start = 0x4806e000,
+ .pa_end = 0x4806e0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_uart4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_uart4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
- &omap44xx_l4_cfg__usb_tll_hs,
+static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
+ {
+ .pa_start = 0x4a0a9000,
+ .pa_end = 0x4a0a93ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
};
-static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
- .name = "usb_tll_hs",
- .class = &omap44xx_usb_tll_hs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .main_clk = "usb_tll_hs_ick",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
+/* l4_cfg -> usb_host_fs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_usb_host_fs_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_usb_host_fs_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
+ {
+ .name = "uhh",
+ .pa_start = 0x4a064000,
+ .pa_end = 0x4a0647ff,
+ .flags = ADDR_TYPE_RT
},
- .mpu_irqs = omap44xx_usb_tll_hs_irqs,
- .slaves = omap44xx_usb_tll_hs_slaves,
- .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
+ {
+ .name = "ohci",
+ .pa_start = 0x4a064800,
+ .pa_end = 0x4a064bff,
+ },
+ {
+ .name = "ehci",
+ .pa_start = 0x4a064c00,
+ .pa_end = 0x4a064fff,
+ },
+ {}
+};
+
+/* l4_cfg -> usb_host_hs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_usb_host_hs_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_usb_host_hs_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
+ {
+ .pa_start = 0x4a0ab000,
+ .pa_end = 0x4a0ab003,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> usb_otg_hs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_usb_otg_hs_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_usb_otg_hs_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
+ {
+ .name = "tll",
+ .pa_start = 0x4a062000,
+ .pa_end = 0x4a063fff,
+ .flags = ADDR_TYPE_RT
+ },
+ {}
+};
+
+/* l4_cfg -> usb_tll_hs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_usb_tll_hs_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_usb_tll_hs_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
+ {
+ .pa_start = 0x4a314000,
+ .pa_end = 0x4a31407f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_wd_timer2_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_wd_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
+ {
+ .pa_start = 0x40130000,
+ .pa_end = 0x4013007f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> wd_timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_wd_timer3_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_wd_timer3_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
+ {
+ .pa_start = 0x49030000,
+ .pa_end = 0x4903007f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_abe -> wd_timer3 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_wd_timer3_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_wd_timer3_dma_addrs,
+ .user = OCP_USER_SDMA,
};
-static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
-
- /* dmm class */
- &omap44xx_dmm_hwmod,
-
- /* emif_fw class */
- &omap44xx_emif_fw_hwmod,
-
- /* l3 class */
- &omap44xx_l3_instr_hwmod,
- &omap44xx_l3_main_1_hwmod,
- &omap44xx_l3_main_2_hwmod,
- &omap44xx_l3_main_3_hwmod,
-
- /* l4 class */
- &omap44xx_l4_abe_hwmod,
- &omap44xx_l4_cfg_hwmod,
- &omap44xx_l4_per_hwmod,
- &omap44xx_l4_wkup_hwmod,
-
- /* mpu_bus class */
- &omap44xx_mpu_private_hwmod,
-
- /* aess class */
-/* &omap44xx_aess_hwmod, */
-
- /* bandgap class */
- &omap44xx_bandgap_hwmod,
-
- /* counter class */
-/* &omap44xx_counter_32k_hwmod, */
-
- /* dma class */
- &omap44xx_dma_system_hwmod,
-
- /* dmic class */
- &omap44xx_dmic_hwmod,
-
- /* dsp class */
- &omap44xx_dsp_hwmod,
- &omap44xx_dsp_c0_hwmod,
-
- /* dss class */
- &omap44xx_dss_hwmod,
- &omap44xx_dss_dispc_hwmod,
- &omap44xx_dss_dsi1_hwmod,
- &omap44xx_dss_dsi2_hwmod,
- &omap44xx_dss_hdmi_hwmod,
- &omap44xx_dss_rfbi_hwmod,
- &omap44xx_dss_venc_hwmod,
-
- /* gpio class */
- &omap44xx_gpio1_hwmod,
- &omap44xx_gpio2_hwmod,
- &omap44xx_gpio3_hwmod,
- &omap44xx_gpio4_hwmod,
- &omap44xx_gpio5_hwmod,
- &omap44xx_gpio6_hwmod,
-
- /* hsi class */
-/* &omap44xx_hsi_hwmod, */
-
- /* i2c class */
- &omap44xx_i2c1_hwmod,
- &omap44xx_i2c2_hwmod,
- &omap44xx_i2c3_hwmod,
- &omap44xx_i2c4_hwmod,
-
- /* ipu class */
- &omap44xx_ipu_hwmod,
- &omap44xx_ipu_c0_hwmod,
- &omap44xx_ipu_c1_hwmod,
-
- /* iss class */
-/* &omap44xx_iss_hwmod, */
-
- /* iva class */
- &omap44xx_iva_hwmod,
- &omap44xx_iva_seq0_hwmod,
- &omap44xx_iva_seq1_hwmod,
-
- /* kbd class */
- &omap44xx_kbd_hwmod,
-
- /* mailbox class */
- &omap44xx_mailbox_hwmod,
-
- /* mcbsp class */
- &omap44xx_mcbsp1_hwmod,
- &omap44xx_mcbsp2_hwmod,
- &omap44xx_mcbsp3_hwmod,
- &omap44xx_mcbsp4_hwmod,
-
- /* mcpdm class */
- &omap44xx_mcpdm_hwmod,
-
- /* mcspi class */
- &omap44xx_mcspi1_hwmod,
- &omap44xx_mcspi2_hwmod,
- &omap44xx_mcspi3_hwmod,
- &omap44xx_mcspi4_hwmod,
-
- /* mmc class */
- &omap44xx_mmc1_hwmod,
- &omap44xx_mmc2_hwmod,
- &omap44xx_mmc3_hwmod,
- &omap44xx_mmc4_hwmod,
- &omap44xx_mmc5_hwmod,
-
- /* mpu class */
- &omap44xx_mpu_hwmod,
-
- /* smartreflex class */
- &omap44xx_smartreflex_core_hwmod,
- &omap44xx_smartreflex_iva_hwmod,
- &omap44xx_smartreflex_mpu_hwmod,
-
- /* spinlock class */
- &omap44xx_spinlock_hwmod,
-
- /* timer class */
- &omap44xx_timer1_hwmod,
- &omap44xx_timer2_hwmod,
- &omap44xx_timer3_hwmod,
- &omap44xx_timer4_hwmod,
- &omap44xx_timer5_hwmod,
- &omap44xx_timer6_hwmod,
- &omap44xx_timer7_hwmod,
- &omap44xx_timer8_hwmod,
- &omap44xx_timer9_hwmod,
- &omap44xx_timer10_hwmod,
- &omap44xx_timer11_hwmod,
-
- /* uart class */
- &omap44xx_uart1_hwmod,
- &omap44xx_uart2_hwmod,
- &omap44xx_uart3_hwmod,
- &omap44xx_uart4_hwmod,
-
- /* usb host class */
- &omap44xx_usb_host_hs_hwmod,
- &omap44xx_usb_tll_hs_hwmod,
-
- /* usb_otg_hs class */
- &omap44xx_usb_otg_hs_hwmod,
-
- /* wd_timer class */
- &omap44xx_wd_timer2_hwmod,
- &omap44xx_wd_timer3_hwmod,
+static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
+ &omap44xx_c2c__c2c_target_fw,
+ &omap44xx_l4_cfg__c2c_target_fw,
+ &omap44xx_l3_main_1__dmm,
+ &omap44xx_mpu__dmm,
+ &omap44xx_c2c__emif_fw,
+ &omap44xx_dmm__emif_fw,
+ &omap44xx_l4_cfg__emif_fw,
+ &omap44xx_iva__l3_instr,
+ &omap44xx_l3_main_3__l3_instr,
+ &omap44xx_ocp_wp_noc__l3_instr,
+ &omap44xx_dsp__l3_main_1,
+ &omap44xx_dss__l3_main_1,
+ &omap44xx_l3_main_2__l3_main_1,
+ &omap44xx_l4_cfg__l3_main_1,
+ &omap44xx_mmc1__l3_main_1,
+ &omap44xx_mmc2__l3_main_1,
+ &omap44xx_mpu__l3_main_1,
+ &omap44xx_c2c_target_fw__l3_main_2,
+ &omap44xx_debugss__l3_main_2,
+ &omap44xx_dma_system__l3_main_2,
+ &omap44xx_fdif__l3_main_2,
+ &omap44xx_gpu__l3_main_2,
+ &omap44xx_hsi__l3_main_2,
+ &omap44xx_ipu__l3_main_2,
+ &omap44xx_iss__l3_main_2,
+ &omap44xx_iva__l3_main_2,
+ &omap44xx_l3_main_1__l3_main_2,
+ &omap44xx_l4_cfg__l3_main_2,
+ &omap44xx_usb_host_fs__l3_main_2,
+ &omap44xx_usb_host_hs__l3_main_2,
+ &omap44xx_usb_otg_hs__l3_main_2,
+ &omap44xx_l3_main_1__l3_main_3,
+ &omap44xx_l3_main_2__l3_main_3,
+ &omap44xx_l4_cfg__l3_main_3,
+ &omap44xx_aess__l4_abe,
+ &omap44xx_dsp__l4_abe,
+ &omap44xx_l3_main_1__l4_abe,
+ &omap44xx_mpu__l4_abe,
+ &omap44xx_l3_main_1__l4_cfg,
+ &omap44xx_l3_main_2__l4_per,
+ &omap44xx_l4_cfg__l4_wkup,
+ &omap44xx_mpu__mpu_private,
+ &omap44xx_l4_cfg__ocp_wp_noc,
+ &omap44xx_l4_abe__aess,
+ &omap44xx_l4_abe__aess_dma,
+ &omap44xx_l3_main_2__c2c,
+ &omap44xx_l4_wkup__counter_32k,
+ &omap44xx_l4_cfg__ctrl_module_core,
+ &omap44xx_l4_cfg__ctrl_module_pad_core,
+ &omap44xx_l4_wkup__ctrl_module_wkup,
+ &omap44xx_l4_wkup__ctrl_module_pad_wkup,
+ &omap44xx_l3_instr__debugss,
+ &omap44xx_l4_cfg__dma_system,
+ &omap44xx_l4_abe__dmic,
+ &omap44xx_l4_abe__dmic_dma,
+ &omap44xx_dsp__iva,
+ &omap44xx_dsp__sl2if,
+ &omap44xx_l4_cfg__dsp,
+ &omap44xx_l3_main_2__dss,
+ &omap44xx_l4_per__dss,
+ &omap44xx_l3_main_2__dss_dispc,
+ &omap44xx_l4_per__dss_dispc,
+ &omap44xx_l3_main_2__dss_dsi1,
+ &omap44xx_l4_per__dss_dsi1,
+ &omap44xx_l3_main_2__dss_dsi2,
+ &omap44xx_l4_per__dss_dsi2,
+ &omap44xx_l3_main_2__dss_hdmi,
+ &omap44xx_l4_per__dss_hdmi,
+ &omap44xx_l3_main_2__dss_rfbi,
+ &omap44xx_l4_per__dss_rfbi,
+ &omap44xx_l3_main_2__dss_venc,
+ &omap44xx_l4_per__dss_venc,
+ &omap44xx_l4_per__elm,
+ &omap44xx_emif_fw__emif1,
+ &omap44xx_emif_fw__emif2,
+ &omap44xx_l4_cfg__fdif,
+ &omap44xx_l4_wkup__gpio1,
+ &omap44xx_l4_per__gpio2,
+ &omap44xx_l4_per__gpio3,
+ &omap44xx_l4_per__gpio4,
+ &omap44xx_l4_per__gpio5,
+ &omap44xx_l4_per__gpio6,
+ &omap44xx_l3_main_2__gpmc,
+ &omap44xx_l3_main_2__gpu,
+ &omap44xx_l4_per__hdq1w,
+ &omap44xx_l4_cfg__hsi,
+ &omap44xx_l4_per__i2c1,
+ &omap44xx_l4_per__i2c2,
+ &omap44xx_l4_per__i2c3,
+ &omap44xx_l4_per__i2c4,
+ &omap44xx_l3_main_2__ipu,
+ &omap44xx_l3_main_2__iss,
+ &omap44xx_iva__sl2if,
+ &omap44xx_l3_main_2__iva,
+ &omap44xx_l4_wkup__kbd,
+ &omap44xx_l4_cfg__mailbox,
+ &omap44xx_l4_abe__mcasp,
+ &omap44xx_l4_abe__mcasp_dma,
+ &omap44xx_l4_abe__mcbsp1,
+ &omap44xx_l4_abe__mcbsp1_dma,
+ &omap44xx_l4_abe__mcbsp2,
+ &omap44xx_l4_abe__mcbsp2_dma,
+ &omap44xx_l4_abe__mcbsp3,
+ &omap44xx_l4_abe__mcbsp3_dma,
+ &omap44xx_l4_per__mcbsp4,
+ &omap44xx_l4_abe__mcpdm,
+ &omap44xx_l4_abe__mcpdm_dma,
+ &omap44xx_l4_per__mcspi1,
+ &omap44xx_l4_per__mcspi2,
+ &omap44xx_l4_per__mcspi3,
+ &omap44xx_l4_per__mcspi4,
+ &omap44xx_l4_per__mmc1,
+ &omap44xx_l4_per__mmc2,
+ &omap44xx_l4_per__mmc3,
+ &omap44xx_l4_per__mmc4,
+ &omap44xx_l4_per__mmc5,
+ &omap44xx_l3_main_2__ocmc_ram,
+ &omap44xx_l4_cfg__ocp2scp_usb_phy,
+ &omap44xx_mpu_private__prcm_mpu,
+ &omap44xx_l4_wkup__cm_core_aon,
+ &omap44xx_l4_cfg__cm_core,
+ &omap44xx_l4_wkup__prm,
+ &omap44xx_l4_wkup__scrm,
+ &omap44xx_l3_main_2__sl2if,
+ &omap44xx_l4_abe__slimbus1,
+ &omap44xx_l4_abe__slimbus1_dma,
+ &omap44xx_l4_per__slimbus2,
+ &omap44xx_l4_cfg__smartreflex_core,
+ &omap44xx_l4_cfg__smartreflex_iva,
+ &omap44xx_l4_cfg__smartreflex_mpu,
+ &omap44xx_l4_cfg__spinlock,
+ &omap44xx_l4_wkup__timer1,
+ &omap44xx_l4_per__timer2,
+ &omap44xx_l4_per__timer3,
+ &omap44xx_l4_per__timer4,
+ &omap44xx_l4_abe__timer5,
+ &omap44xx_l4_abe__timer5_dma,
+ &omap44xx_l4_abe__timer6,
+ &omap44xx_l4_abe__timer6_dma,
+ &omap44xx_l4_abe__timer7,
+ &omap44xx_l4_abe__timer7_dma,
+ &omap44xx_l4_abe__timer8,
+ &omap44xx_l4_abe__timer8_dma,
+ &omap44xx_l4_per__timer9,
+ &omap44xx_l4_per__timer10,
+ &omap44xx_l4_per__timer11,
+ &omap44xx_l4_per__uart1,
+ &omap44xx_l4_per__uart2,
+ &omap44xx_l4_per__uart3,
+ &omap44xx_l4_per__uart4,
+ &omap44xx_l4_cfg__usb_host_fs,
+ &omap44xx_l4_cfg__usb_host_hs,
+ &omap44xx_l4_cfg__usb_otg_hs,
+ &omap44xx_l4_cfg__usb_tll_hs,
+ &omap44xx_l4_wkup__wd_timer2,
+ &omap44xx_l4_abe__wd_timer3,
+ &omap44xx_l4_abe__wd_timer3_dma,
NULL,
};
int __init omap44xx_hwmod_init(void)
{
- return omap_hwmod_register(omap44xx_hwmods);
+ return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
}
#include "display.h"
/* Common address space across OMAP2xxx */
-extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
/* Common address space across OMAP2xxx/3xxx */
extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
+extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
/* Common IP block data across OMAP2xxx */
extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
+extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
+extern struct omap_hwmod omap2xxx_l3_main_hwmod;
+extern struct omap_hwmod omap2xxx_l4_core_hwmod;
+extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
+extern struct omap_hwmod omap2xxx_mpu_hwmod;
+extern struct omap_hwmod omap2xxx_iva_hwmod;
+extern struct omap_hwmod omap2xxx_timer1_hwmod;
+extern struct omap_hwmod omap2xxx_timer2_hwmod;
+extern struct omap_hwmod omap2xxx_timer3_hwmod;
+extern struct omap_hwmod omap2xxx_timer4_hwmod;
+extern struct omap_hwmod omap2xxx_timer5_hwmod;
+extern struct omap_hwmod omap2xxx_timer6_hwmod;
+extern struct omap_hwmod omap2xxx_timer7_hwmod;
+extern struct omap_hwmod omap2xxx_timer8_hwmod;
+extern struct omap_hwmod omap2xxx_timer9_hwmod;
+extern struct omap_hwmod omap2xxx_timer10_hwmod;
+extern struct omap_hwmod omap2xxx_timer11_hwmod;
+extern struct omap_hwmod omap2xxx_timer12_hwmod;
+extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
+extern struct omap_hwmod omap2xxx_uart1_hwmod;
+extern struct omap_hwmod omap2xxx_uart2_hwmod;
+extern struct omap_hwmod omap2xxx_uart3_hwmod;
+extern struct omap_hwmod omap2xxx_dss_core_hwmod;
+extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
+extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
+extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
+extern struct omap_hwmod omap2xxx_gpio1_hwmod;
+extern struct omap_hwmod omap2xxx_gpio2_hwmod;
+extern struct omap_hwmod omap2xxx_gpio3_hwmod;
+extern struct omap_hwmod omap2xxx_gpio4_hwmod;
+extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
+extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
+extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
+
+/* Common interface data across OMAP2xxx */
+extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
+extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
+extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
/* Common IP block data */
extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
+extern struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[];
/* OMAP hwmod classes - forward declarations */
extern struct omap_hwmod_class l3_hwmod_class;
extern struct omap_hwmod_class omap2_dispc_hwmod_class;
extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
extern struct omap_hwmod_class omap2_venc_hwmod_class;
+extern struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc;
+extern struct omap_hwmod_class omap2_hdq1w_class;
extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
return ret;
}
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
-{
- if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
- pwrdm_wait_transition(clkdm->pwrdm.ptr);
- return pwrdm_state_switch(clkdm->pwrdm.ptr);
- }
-
- return -EINVAL;
-}
-
int pwrdm_pre_transition(void)
{
pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
int pwrdm_wait_transition(struct powerdomain *pwrdm);
int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
int pwrdm_pre_transition(void);
int pwrdm_post_transition(void);
int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
#define OMAP24XX_ST_GPIOS_SHIFT 2
#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
+#define OMAP24XX_ST_32KSYNC_SHIFT 1
+#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
#define OMAP24XX_ST_GPT1_SHIFT 0
#define OMAP24XX_ST_GPT1_MASK (1 << 0)
#define OMAP3430_ST_SR1_MASK (1 << 6)
#define OMAP3430_ST_GPIO1_SHIFT 3
#define OMAP3430_ST_GPIO1_MASK (1 << 3)
+#define OMAP3430_ST_32KSYNC_SHIFT 2
+#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
#define OMAP3430_ST_GPT12_SHIFT 1
#define OMAP3430_ST_GPT12_MASK (1 << 1)
#define OMAP3430_ST_GPT1_SHIFT 0
extern void __iomem *prm_base;
extern void __iomem *cm_base;
extern void __iomem *cm2_base;
+extern void __iomem *prcm_mpu_base;
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
+extern void omap_prm_base_init(void);
+extern void omap_cm_base_init(void);
+#else
+static inline void omap_prm_base_init(void)
+{
+}
+static inline void omap_cm_base_init(void)
+{
+}
+#endif
/**
* struct omap_prcm_irq - describes a PRCM interrupt bit
void __iomem *prm_base;
void __iomem *cm_base;
void __iomem *cm2_base;
+void __iomem *prcm_mpu_base;
#define MAX_MODULE_ENABLE_WAIT 100000
cm_base = omap2_globals->cm;
if (omap2_globals->cm2)
cm2_base = omap2_globals->cm2;
+ if (omap2_globals->prcm_mpu)
+ prcm_mpu_base = omap2_globals->prcm_mpu;
+
+ if (cpu_is_omap44xx()) {
+ omap_prm_base_init();
+ omap_cm_base_init();
+ }
}
#include "iomap.h"
#include "common.h"
+#include "prcm-common.h"
#include "prm44xx.h"
#include "prminst44xx.h"
#include "prm-regbits-44xx.h"
#include "prcm44xx.h"
#include "prcm_mpu44xx.h"
-static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
- [OMAP4430_INVALID_PRCM_PARTITION] = 0,
- [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE,
- [OMAP4430_CM1_PARTITION] = 0,
- [OMAP4430_CM2_PARTITION] = 0,
- [OMAP4430_SCRM_PARTITION] = 0,
- [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE,
-};
+static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
+
+/**
+ * omap_prm_base_init - Populates the prm partitions
+ *
+ * Populates the base addresses of the _prm_bases
+ * array used for read/write of prm module registers.
+ */
+void omap_prm_base_init(void)
+{
+ _prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
+ _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+}
/* Read a register in a PRM instance */
u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_prm_bases[part]);
- return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst +
- idx));
+ return __raw_readl(_prm_bases[part] + inst + idx);
}
/* Write into a register in a PRM instance */
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_prm_bases[part]);
- __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx));
+ __raw_writel(val, _prm_bases[part] + inst + idx);
}
/* Read-modify-write a register in PRM. Caller must lock */
{
char name[10]; /* 10 = sizeof("gptXX_Xck0") */
struct omap_hwmod *oh;
+ struct resource irq_rsrc, mem_rsrc;
size_t size;
int res = 0;
+ int r;
sprintf(name, "timer%d", gptimer_id);
omap_hwmod_setup_one(name);
if (!oh)
return -ENODEV;
- timer->irq = oh->mpu_irqs[0].irq;
- timer->phys_base = oh->slaves[0]->addr->pa_start;
- size = oh->slaves[0]->addr->pa_end - timer->phys_base;
+ r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
+ if (r)
+ return -ENXIO;
+ timer->irq = irq_rsrc.start;
+
+ r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
+ if (r)
+ return -ENXIO;
+ timer->phys_base = mem_rsrc.start;
+ size = mem_rsrc.end - mem_rsrc.start;
/* Static mapping, never released */
timer->io_base = ioremap(timer->phys_base, size);
if (IS_ERR(timer->fclk))
return -ENODEV;
- sprintf(name, "gpt%d_ick", gptimer_id);
- timer->iclk = clk_get(NULL, name);
- if (IS_ERR(timer->iclk)) {
- clk_put(timer->fclk);
- return -ENODEV;
- }
-
omap_hwmod_enable(oh);
sys_timer_reserved |= (1 << (gptimer_id - 1));
#include <plat/omap_hwmod.h>
#include "wd_timer.h"
+#include "common.h"
/*
* In order to avoid any assumptions from bootloader regarding WDT
#define OMAP_WDT_WPS 0x34
#define OMAP_WDT_SPR 0x48
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT 10000
int omap2_wd_timer_disable(struct omap_hwmod *oh)
{
return 0;
}
+/**
+ * omap2_wdtimer_reset - reset and disable the WDTIMER IP block
+ * @oh: struct omap_hwmod *
+ *
+ * After the WDTIMER IP blocks are reset on OMAP2/3, we must also take
+ * care to execute the special watchdog disable sequence. This is
+ * because the watchdog is re-armed upon OCP softreset. (On OMAP4,
+ * this behavior was apparently changed and the watchdog is no longer
+ * re-armed after an OCP soft-reset.) Returns -ETIMEDOUT if the reset
+ * did not complete, or 0 upon success.
+ *
+ * XXX Most of this code should be moved to the omap_hwmod.c layer
+ * during a normal merge window. omap_hwmod_softreset() should be
+ * renamed to omap_hwmod_set_ocp_softreset(), and omap_hwmod_softreset()
+ * should call the hwmod _ocp_softreset() code.
+ */
+int omap2_wd_timer_reset(struct omap_hwmod *oh)
+{
+ int c = 0;
+
+ /* Write to the SOFTRESET bit */
+ omap_hwmod_softreset(oh);
+
+ /* Poll on RESETDONE bit */
+ omap_test_timeout((omap_hwmod_read(oh,
+ oh->class->sysc->syss_offs)
+ & SYSS_RESETDONE_MASK),
+ MAX_MODULE_SOFTRESET_WAIT, c);
+
+ if (oh->class->sysc->srst_udelay)
+ udelay(oh->class->sysc->srst_udelay);
+
+ if (c == MAX_MODULE_SOFTRESET_WAIT)
+ pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+ __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+ else
+ pr_debug("%s: %s: softreset in %d usec\n", __func__,
+ oh->name, c);
+
+ return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
+ omap2_wd_timer_disable(oh);
+}
#include <plat/omap_hwmod.h>
extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
+extern int omap2_wd_timer_reset(struct omap_hwmod *oh);
#endif
#define CK_243X (1 << 5) /* 243x, 253x */
#define CK_3430ES1 (1 << 6) /* 34xxES1 only */
#define CK_3430ES2PLUS (1 << 7) /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_3505 (1 << 8)
-#define CK_3517 (1 << 9)
+#define CK_AM35XX (1 << 9) /* Sitara AM35xx */
#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
#define CK_443X (1 << 11)
#define CK_TI816X (1 << 12)
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
-#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */
#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
unsigned long phys_base;
int id;
int irq;
- struct clk *iclk, *fclk;
+ struct clk *fclk;
void __iomem *io_base;
void __iomem *sys_stat; /* TISTAT timer status */
--- /dev/null
+/*
+ * Shared macros and function prototypes for the HDQ1W/1-wire IP block
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+#ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H
+#define ARCH_ARM_MACH_OMAP2_HDQ1W_H
+
+#include <plat/omap_hwmod.h>
+
+/*
+ * XXX A future cleanup patch should modify
+ * drivers/w1/masters/omap_hdq.c to use these macros
+ */
+#define HDQ_CTRL_STATUS_OFFSET 0x0c
+#define HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT 5
+
+
+extern int omap_hdq1w_reset(struct omap_hwmod *oh);
+
+#endif
#include <linux/mmc/host.h>
#include <plat/board.h>
+#include <plat/omap_hwmod.h>
#define OMAP15XX_NR_MMC 1
#define OMAP16XX_NR_MMC 2
}
#endif
+
+extern int omap_msdi_reset(struct omap_hwmod *oh);
+
#endif
*/
#define OCP_USER_MPU (1 << 0)
#define OCP_USER_SDMA (1 << 1)
+#define OCP_USER_DSP (1 << 2)
+#define OCP_USER_IVA (1 << 3)
/* omap_hwmod_ocp_if.flags bits */
#define OCPIF_SWSUP_IDLE (1 << 0)
#define OCPIF_CAN_BURST (1 << 1)
+/* omap_hwmod_ocp_if._int_flags possibilities */
+#define _OCPIF_INT_FLAGS_REGISTERED (1 << 0)
+
+
/**
* struct omap_hwmod_ocp_if - OCP interface data
* @master: struct omap_hwmod that initiates OCP transactions on this link
* @width: OCP data width
* @user: initiators using this interface (see OCP_USER_* macros above)
* @flags: OCP interface flags (see OCPIF_* macros above)
+ * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above)
*
* It may also be useful to add a tag_cnt field for OCP2.x devices.
*
u8 width;
u8 user;
u8 flags;
+ u8 _int_flags;
};
* then this field has to be populated with the correct offset structure.
*/
struct omap_hwmod_class_sysconfig {
- u16 rev_offs;
- u16 sysc_offs;
- u16 syss_offs;
+ u32 rev_offs;
+ u32 sysc_offs;
+ u32 syss_offs;
u16 sysc_flags;
struct omap_hwmod_sysc_fields *sysc_fields;
u8 srst_udelay;
int (*reset)(struct omap_hwmod *oh);
};
+/**
+ * struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs
+ * @ocp_if: OCP interface structure record pointer
+ * @node: list_head pointing to next struct omap_hwmod_link in a list
+ */
+struct omap_hwmod_link {
+ struct omap_hwmod_ocp_if *ocp_if;
+ struct list_head node;
+};
+
/**
* struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
* @name: name of the hwmod
* @_clk: pointer to the main struct clk (filled in at runtime)
* @opt_clks: other device clocks that drivers can request (0..*)
* @voltdm: pointer to voltage domain (filled in at runtime)
- * @masters: ptr to array of OCP ifs that this hwmod can initiate on
- * @slaves: ptr to array of OCP ifs that this hwmod can respond on
* @dev_attr: arbitrary device attributes that can be passed to the driver
* @_sysc_cache: internal-use hwmod flags
* @_mpu_rt_va: cached register target start address (internal use)
- * @_mpu_port_index: cached MPU register target slave ID (internal use)
+ * @_mpu_port: cached MPU register target slave (internal use)
* @opt_clks_cnt: number of @opt_clks
* @master_cnt: number of @master entries
* @slaves_cnt: number of @slave entries
*
* Parameter names beginning with an underscore are managed internally by
* the omap_hwmod code and should not be set during initialization.
+ *
+ * @masters and @slaves are now deprecated.
*/
struct omap_hwmod {
const char *name;
struct omap_hwmod_opt_clk *opt_clks;
char *clkdm_name;
struct clockdomain *clkdm;
- struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
- struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
+ struct list_head master_ports; /* connect to *_IA */
+ struct list_head slave_ports; /* connect to *_TA */
void *dev_attr;
u32 _sysc_cache;
void __iomem *_mpu_rt_va;
spinlock_t _lock;
struct list_head node;
+ struct omap_hwmod_ocp_if *_mpu_port;
u16 flags;
- u8 _mpu_port_index;
u8 response_lat;
u8 rst_lines_cnt;
u8 opt_clks_cnt;
u8 _postsetup_state;
};
-int omap_hwmod_register(struct omap_hwmod **ohs);
struct omap_hwmod *omap_hwmod_lookup(const char *name);
int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
void *data);
int omap_hwmod_count_resources(struct omap_hwmod *oh);
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
+int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
+ const char *name, struct resource *res);
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
+extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
+
#endif
projects / deliverable / linux.git / commitdiff
