mmc: sdhci-esdhc-imx: fix mmc ddr mode regression issue

It's caused by the platform driver was still using MMC_TIMING_UHS_DDR50
for MMC DDR mode which needs update too.

Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Reported-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
[Ulf Hansson] Resolved conflict
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 4866d802f9e277477d33a9bddf20604058de107a..ccec0e32590f6b5f9336f0fc77df279e429756a2 100644 (file)
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -852,6 +852,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
        case MMC_TIMING_MMC_HS200:
                break;
        case MMC_TIMING_UHS_DDR50:
+       case MMC_TIMING_MMC_DDR52:
                writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
                                ESDHC_MIX_CTRL_DDREN,
                                host->ioaddr + ESDHC_MIX_CTRL);