Merge tag 'renesas-dt-fixes-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel...

From Simon Horman:
Renesas ARM Based SoC DT Fixes for v3.14

Revert the addition of SSI clocks to DT for the
r8a7790 (R-Car H2) and r8a7791 (R-Car M2) SoCs.

Unfortunately these patches prevent booting the
r8a7790-based Lager board and r8a7791-based Koelsch board
to the point where a serial output is available.

A solution to this problem is being sought but has not
yet been finalised so in the mean time revert the changes.

* tag 'renesas-dt-fixes-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  Revert "ARM: shmobile: r8a7791: Add SSI clocks in device tree"
  Revert "ARM: shmobile: r8a7790: Add SSI clocks in device tree"

Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index c5417dafca0d5b6278dd1dc9884e83bc2d97c70e..a1791250bf4b354148961f867568a5879ff0cd43 100644 (file)
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -626,25 +626,5 @@
                        clock-output-names =
                                "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
                };
-               mstp10_clks: mstp10_clks@e6150998 {
-                       compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
-                       reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
-                       clocks = <&p_clk>, <&mstp10_clks R8A7790_CLK_SSI>,
-                                <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
-                                <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
-                                <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
-                                <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>,
-                                <&mstp10_clks R8A7790_CLK_SSI>;
-                       #clock-cells = <1>;
-                       renesas,clock-indices = <
-                               R8A7790_CLK_SSI R8A7790_CLK_SSI9 R8A7790_CLK_SSI8
-                               R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
-                               R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2
-                               R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
-                       >;
-                       clock-output-names =
-                               "ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
-                               "ssi4", "ssi3", "ssi2", "ssi1", "ssi0";
-               };
        };
 };

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e92c1f7aedd055a2a409adb3d5f61e15795f804c..19c65509a22d8b10cc48e667fb747bdda0d6ee1e 100644 (file)
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -495,26 +495,6 @@
                                "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
                                "i2c2", "i2c1", "i2c0";
                };
-               mstp10_clks: mstp10_clks@e6150998 {
-                       compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-                       reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
-                       clocks = <&p_clk>, <&mstp10_clks R8A7791_CLK_SSI>,
-                                <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
-                                <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
-                                <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
-                                <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
-                                <&mstp10_clks R8A7791_CLK_SSI>;
-                       #clock-cells = <1>;
-                       renesas,clock-indices = <
-                               R8A7791_CLK_SSI R8A7791_CLK_SSI9 R8A7791_CLK_SSI8
-                               R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
-                               R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2
-                               R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
-                       >;
-                       clock-output-names =
-                               "ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
-                               "ssi4", "ssi3", "ssi2", "ssi1", "ssi0";
-               };
                mstp11_clks: mstp11_clks@e615099c {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;

diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index dbb262a3e7a60b321ed09e6c68c1ce26c0f8ac3d..859e9be511d9251b7e7033a5a9489a9091237b5f 100644 (file)
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -104,17 +104,4 @@
 #define R8A7790_CLK_I2C1               30
 #define R8A7790_CLK_I2C0               31
 
-/* MSTP10 */
-#define R8A7790_CLK_SSI                        5
-#define R8A7790_CLK_SSI9               6
-#define R8A7790_CLK_SSI8               7
-#define R8A7790_CLK_SSI7               8
-#define R8A7790_CLK_SSI6               9
-#define R8A7790_CLK_SSI5               10
-#define R8A7790_CLK_SSI4               11
-#define R8A7790_CLK_SSI3               12
-#define R8A7790_CLK_SSI2               13
-#define R8A7790_CLK_SSI1               14
-#define R8A7790_CLK_SSI0               15
-
 #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */

diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index 1c8f00d0d88b25f0578bd413def76cbd8067f054..30f82f286e295df3423dd6729ef48918c80683c2 100644 (file)
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -103,19 +103,6 @@
 #define R8A7791_CLK_I2C1               30
 #define R8A7791_CLK_I2C0               31
 
-/* MSTP10 */
-#define R8A7791_CLK_SSI                        5
-#define R8A7791_CLK_SSI9               6
-#define R8A7791_CLK_SSI8               7
-#define R8A7791_CLK_SSI7               8
-#define R8A7791_CLK_SSI6               9
-#define R8A7791_CLK_SSI5               10
-#define R8A7791_CLK_SSI4               11
-#define R8A7791_CLK_SSI3               12
-#define R8A7791_CLK_SSI2               13
-#define R8A7791_CLK_SSI1               14
-#define R8A7791_CLK_SSI0               15
-
 /* MSTP11 */
 #define R8A7791_CLK_SCIFA3             6
 #define R8A7791_CLK_SCIFA4             7