ARM: dts: imx6qdl: Add power-domain information to gpc node

The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled, and a list of phandles to all clocks that must be
enabled during powerup for reset propagation.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 3a2d05432d704e3789a9db12c3c50dfa66cbdf5d..76f4997d86fcd3fb24fcdf84a3f4dcef5a085085 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -700,6 +700,14 @@
                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 90 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-parent = <&intc>;
+                               pu-supply = <&reg_pu>;
+                               clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+                                        <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+                                        <&clks IMX6QDL_CLK_GPU2D_CORE>,
+                                        <&clks IMX6QDL_CLK_GPU2D_AXI>,
+                                        <&clks IMX6QDL_CLK_OPENVG_AXI>,
+                                        <&clks IMX6QDL_CLK_VPU_AXI>;
+                               #power-domain-cells = <1>;
                        };
 
                        gpr: iomuxc-gpr@020e0000 {