ARM: ux500: define CPU topology

The CPU topology is unspecified for Ux500 but will be needed
for things like CoreSight. Let's just add it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index bfd3f1c734b8d84dec4a622032e1b29efa07b83d..bd6bd0926931f5513fa93e638291b6c514b3a283 100644 (file)
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -22,6 +22,32 @@
                interrupt-parent = <&intc>;
                ranges;
 
+               cpus {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       cpu-map {
+                               cluster0 {
+                                       core0 {
+                                               cpu = <&CPU0>;
+                                       };
+                                       core1 {
+                                               cpu = <&CPU1>;
+                                       };
+                               };
+                       };
+                       CPU0: cpu@0 {
+                               device_type = "cpu";
+                               compatible = "arm,cortex-a9";
+                               reg = <0>;
+                       };
+                       CPU1: cpu@1 {
+                               device_type = "cpu";
+                               compatible = "arm,cortex-a9";
+                               reg = <1>;
+                       };
+               };
+
                intc: interrupt-controller@a0411000 {
                        compatible = "arm,cortex-a9-gic";
                        #interrupt-cells = <3>;