ASoC: fsl_ssi: enable IPG clock during AC'97 reg access

IPG clock have to be enabled during AC'97 CODEC register
access in fsl_ssi driver.

Signed-off-by: Maciej Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index c7647e066cfd76b07f6b1acd4d2a68ac04bae3bc..9c46c7dc0f2041d6e939e4f1572a60c1cb1b16a7 100644 (file)
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -1127,10 +1127,17 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
        struct regmap *regs = fsl_ac97_data->regs;
        unsigned int lreg;
        unsigned int lval;
+       int ret;
 
        if (reg > 0x7f)
                return;
 
+       ret = clk_prepare_enable(fsl_ac97_data->clk);
+       if (ret) {
+               pr_err("ac97 write clk_prepare_enable failed: %d\n",
+                       ret);
+               return;
+       }
 
        lreg = reg <<  12;
        regmap_write(regs, CCSR_SSI_SACADD, lreg);
@@ -1141,6 +1148,8 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
        regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
                        CCSR_SSI_SACNT_WR);
        udelay(100);
+
+       clk_disable_unprepare(fsl_ac97_data->clk);
 }
 
 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
@@ -1151,6 +1160,14 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
        unsigned short val = -1;
        u32 reg_val;
        unsigned int lreg;
+       int ret;
+
+       ret = clk_prepare_enable(fsl_ac97_data->clk);
+       if (ret) {
+               pr_err("ac97 read clk_prepare_enable failed: %d\n",
+                       ret);
+               return -1;
+       }
 
        lreg = (reg & 0x7f) <<  12;
        regmap_write(regs, CCSR_SSI_SACADD, lreg);
@@ -1162,6 +1179,8 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
        regmap_read(regs, CCSR_SSI_SACDAT, &reg_val);
        val = (reg_val >> 4) & 0xffff;
 
+       clk_disable_unprepare(fsl_ac97_data->clk);
+
        return val;
 }