ARM: dts: imx27-phytec-phycore-rdk: Add pingrp for SDHC

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index e9a99667614045b33f698a9809d6fcca437f1d17..9997f58a4d146f7cf4b3058a037ebdf973a3d366 100644 (file)
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -50,6 +50,19 @@
                        >;
                };
 
+               pinctrl_sdhc2: sdhc2grp {
+                       fsl,pins = <
+                               MX27_PAD_SD2_CLK__SD2_CLK 0x0
+                               MX27_PAD_SD2_CMD__SD2_CMD 0x0
+                               MX27_PAD_SD2_D0__SD2_D0 0x0
+                               MX27_PAD_SD2_D1__SD2_D1 0x0
+                               MX27_PAD_SD2_D2__SD2_D2 0x0
+                               MX27_PAD_SD2_D3__SD2_D3 0x0
+                               MX27_PAD_SSI3_FS__GPIO3_28      0x0 /* WP */
+                               MX27_PAD_SSI3_RXDAT__GPIO3_29   0x0 /* CD */
+                       >;
+               };
+
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
                                MX27_PAD_UART1_TXD__UART1_TXD 0x0
@@ -77,6 +90,8 @@
 };
 
 &sdhci2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sdhc2>;
        bus-width = <4>;
        cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
        wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;