* Implement remaining bits in VPU_STAT, CMSAR0, CMSAR1, FBRST. Fix COP2 interface

* to VI registers (CFC2/CTC2).
*
* Modified Files:
* 	ChangeLog.sky interp.c sim-main.c sky-pke.h sky-vu.c sky-vu.h

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index f0ba619f7484f11763e95bc9bab8b718053a5255..113a136b63150ec0d6d6902c84e6cdd9c9d88e8d 100644 (file)
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -3440,14 +3440,7 @@ decode_coproc (SIM_DESC sd,
              }
            else /* CFC2 */
              {
-               unsigned_4 data;
-               /* enum + int calculation, argh! */
-               id = VU_REG_MST + 16 * id;
-               if (id >= VU_REG_CMSAR0)
-                 read_vu_special_reg(&vu0_device, id, & data);
-               else
-                 read_vu_misc_reg(&(vu0_device.regs), id, & data);
-               GPR[rt] = EXTEND32(T2H_4(data));
+               GPR[rt] = vu0_read_cop2_register(id);
              }
          }
        else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
@@ -3483,13 +3476,7 @@ decode_coproc (SIM_DESC sd,
              }
            else /* CTC2 */
              {
-               unsigned_4 data = H2T_4(GPR[rt]);
-               /* enum + int calculation, argh! */
-               id = VU_REG_VI + 16 * id;
-               if (id >= VU_REG_CMSAR0)
-                 write_vu_special_reg(&vu0_device, id, & data);
-               else
-                 write_vu_misc_reg(&(vu0_device.regs), id, & data);
+               vu0_write_cop2_register(id, GPR[rt]);
              }
          }
        else if(i_10_0 == 0x3bf) /* VWAITQ */

diff --git a/sim/mips/sky-pke.h b/sim/mips/sky-pke.h
index 728b12bd9829ae50830dbae8ee485f3efd4462d1..a24e772228ffbbe2d7a93977ff4dd9a05eb9de95 100644 (file)
--- a/sim/mips/sky-pke.h
+++ b/sim/mips/sky-pke.h
@@ -53,7 +53,7 @@ typedef unsigned_4 quadword[4];
 #define GPUIF_REG_STAT_APATH_B 10
 
 /* COP2 STAT register */
-#define COP2_REG_STAT_ADDR VPU_STAT
+#define COP2_REG_STAT_ADDR VPU_STAT_ADDR
 #define COP2_REG_STAT_VBS1_E 8
 #define COP2_REG_STAT_VBS1_B 8
 #define COP2_REG_STAT_VBS0_E 0