arm64: dts: hip05: Append gpio nodes

There are two dw GPIO controllers in hip05 peri sub, this patch
adds the corresponding device tree nodes.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index c1b1a32939ed5e131df5e7f7963b90c2053d5659..6319ff3b03ea4d7d411d47a5fecffc4b5a18c80c 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -322,5 +322,43 @@
                        reg-io-width = <4>;
                        status = "disabled";
                };
+
+               peri_gpio0: gpio@802e0000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x0 0x802e0000 0x0 0x10000>;
+                       status = "disabled";
+
+                       porta: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <32>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               peri_gpio1: gpio@802f0000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x0 0x802f0000 0x0 0x10000>;
+                       status = "disabled";
+
+                       portb: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <32>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
        };
 };