drm/i915/skl: Implement WaDisablePartialResolveInVc
authorDamien Lespiau <damien.lespiau@intel.com>
Mon, 9 Feb 2015 19:33:17 +0000 (19:33 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 13 Feb 2015 22:28:34 +0000 (23:28 +0100)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c

index b00d323095af79709a3ad5b704c212e2c431a6ce..b610764768d7528f50fb27da6c14bd11e6290d17 100644 (file)
@@ -1483,6 +1483,7 @@ enum skl_disp_power_wells {
 #define CACHE_MODE_1           0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE    (1<<6)
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE    (1<<6)
+#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1<<1)
 
 #define GEN6_BLITTER_ECOSKPD   0x221d0
 #define   GEN6_BLITTER_LOCK_SHIFT                      16
index ad9d7eb86ef6553029f055e15e8943c88b70e685..29873ff2dd8db156b703bff10fbd27da3a1c53e8 100644 (file)
@@ -981,6 +981,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
        /* Wa4x4STCOptimizationDisable:skl */
        WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
+       /* WaDisablePartialResolveInVc:skl */
+       WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
+
        return 0;
 }
 
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