ARM: imx: clk-imx27: Do not register peripheral clock for SSI

imx ssi block has two types of clocks:

- ipg: bus clock, the clock needed for accessing registers.
- per: peripheral clock, the clock needed for generating the bit rate.

Currently ssi driver only supports slave mode and thus need only to handle
the ipg clock, because the peripheral clock comes from the master codec.

Only register the ipg clock and do not register the peripheral clock for ssi

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 30b3242a7d49b12f1b012ee2c9a7c5aab2ab7217..8e3b6571910654a25320e4be16ac32f2bd6e51a9 100644 (file)
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -278,8 +278,6 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
        clk_register_clkdev(clk[cpu_div], "cpu", NULL);
        clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
-       clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
-       clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
 
        mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);