drm/msm: Set different display size limitation on each target
authorHai Li <hali@codeaurora.org>
Wed, 24 Jun 2015 23:13:40 +0000 (19:13 -0400)
committerRob Clark <robdclark@gmail.com>
Sat, 15 Aug 2015 22:27:14 +0000 (18:27 -0400)
The maximum output width of one pipeline depends on the LayerMixer's
capability. It may be different on each target. Also, MDP5 doesn't
have vertical limitation in one frame, as long as the pixel clock
can be supported.

This change obtains the maximum LM resolution from configuration
table and treat it as the whole pipe's limitation for MDP5. The size
limit on MDP4 is not changed.

Signed-off-by: Hai Li <hali@codeaurora.org>
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
drivers/gpu/drm/msm/msm_drv.c

index 531e4acc2a872f8263b1e124e3e801ff30521e7b..c7b48798b998ff707aa29e33808339fffe7ad625 100644 (file)
@@ -527,6 +527,11 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
                goto fail;
        }
 
+       dev->mode_config.min_width = 0;
+       dev->mode_config.min_height = 0;
+       dev->mode_config.max_width = 2048;
+       dev->mode_config.max_height = 2048;
+
        return kms;
 
 fail:
index fbc58fc0ab681283ebb78d0413804523e40df18d..d42ba9e7978a444741d10391fd2229629ef47880 100644 (file)
@@ -58,6 +58,8 @@ const struct mdp5_cfg_hw msm8x74_config = {
                .count = 5,
                .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
                .nb_stages = 5,
+               .max_width = 2048,
+               .max_height = 0xFFFF,
        },
        .dspp = {
                .count = 3,
@@ -126,6 +128,8 @@ const struct mdp5_cfg_hw apq8084_config = {
                .count = 6,
                .base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 },
                .nb_stages = 5,
+               .max_width = 2048,
+               .max_height = 0xFFFF,
        },
        .dspp = {
                .count = 4,
@@ -187,6 +191,8 @@ const struct mdp5_cfg_hw msm8x16_config = {
                .count = 2, /* LM0 and LM3 */
                .base = { 0x45000, 0x48000 },
                .nb_stages = 5,
+               .max_width = 2048,
+               .max_height = 0xFFFF,
        },
        .dspp = {
                .count = 1,
@@ -248,6 +254,8 @@ const struct mdp5_cfg_hw msm8x94_config = {
                .count = 6,
                .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 },
                .nb_stages = 8,
+               .max_width = 2048,
+               .max_height = 0xFFFF,
        },
        .dspp = {
                .count = 4,
index 69349abe59f2a4a614a9a9379b5c26f232087a3c..8a19d271d18f2264b68a950fc8f348e85a6156ea 100644 (file)
@@ -42,6 +42,8 @@ struct mdp5_sub_block {
 struct mdp5_lm_block {
        MDP5_SUB_BLOCK_DEFINITION;
        uint32_t nb_stages;             /* number of stages per blender */
+       uint32_t max_width;             /* Maximum output resolution */
+       uint32_t max_height;
 };
 
 struct mdp5_ctl_block {
index b82856327841226ffc5269eb1f58f0e4a52094f7..97d9da2175b4650d58d0693aa2b34dcb30e4c279 100644 (file)
@@ -579,6 +579,11 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
                goto fail;
        }
 
+       dev->mode_config.min_width = 0;
+       dev->mode_config.min_height = 0;
+       dev->mode_config.max_width = config->hw->lm.max_width;
+       dev->mode_config.max_height = config->hw->lm.max_height;
+
        return kms;
 
 fail:
index d3467b115e0482a6eca2ebd6a5810e31f69220fa..39ce1920f5f592604bceb8201b76adc67ee36d11 100644 (file)
@@ -331,10 +331,6 @@ static int msm_load(struct drm_device *dev, unsigned long flags)
                }
        }
 
-       dev->mode_config.min_width = 0;
-       dev->mode_config.min_height = 0;
-       dev->mode_config.max_width = 2048;
-       dev->mode_config.max_height = 2048;
        dev->mode_config.funcs = &mode_config_funcs;
 
        ret = drm_vblank_init(dev, priv->num_crtcs);
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