Merge commit 'origin/master' into next
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 24 Mar 2009 02:38:30 +0000 (13:38 +1100)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 24 Mar 2009 02:38:30 +0000 (13:38 +1100)
1  2 
arch/powerpc/include/asm/cputable.h
arch/powerpc/kernel/head_32.S
arch/powerpc/platforms/ps3/Kconfig

index fca161190db434f3432d8733479021e5b9c55918,21172badd708fc4f3d893a526339345f77a11281..80f315e8a421b2f0bde0bb6cc9d931c7fb5d5372
@@@ -145,7 -145,6 +145,7 @@@ extern const char *powerpc_base_platfor
  #define CPU_FTR_USE_TB                        ASM_CONST(0x0000000000000040)
  #define CPU_FTR_L2CSR                 ASM_CONST(0x0000000000000080)
  #define CPU_FTR_601                   ASM_CONST(0x0000000000000100)
 +#define CPU_FTR_DBELL                 ASM_CONST(0x0000000000000200)
  #define CPU_FTR_CAN_NAP                       ASM_CONST(0x0000000000000400)
  #define CPU_FTR_L3CR                  ASM_CONST(0x0000000000000800)
  #define CPU_FTR_L3_DISABLE_NAP                ASM_CONST(0x0000000000001000)
  /* We need to mark all pages as being coherent if we're SMP or we have a
   * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
   * require it for PCI "streaming/prefetch" to work properly.
+  * This is also required by 52xx family.
   */
  #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
-       || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
+       || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
+       || defined(CONFIG_PPC_MPC52xx)
  #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
  #else
  #define CPU_FTR_COMMON                  0
            CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
  #define CPU_FTRS_E500MC       (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
 -          CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE)
 +          CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 +          CPU_FTR_DBELL)
  #define CPU_FTRS_GENERIC_32   (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
  
  /* 64-bit CPUs */
index f8c2e6b6f457dabda37f54da8250548534bc04d6,d794a637e421ffaf59dad48cdbbe95e832f3952b..d0bad4b93a9cadf970b4f58cf48fd6f7edf60bda
@@@ -108,21 -108,18 +108,21 @@@ __start
   * because OF may have I/O devices mapped into that area
   * (particularly on CHRP).
   */
 -#ifdef CONFIG_PPC_MULTIPLATFORM
        cmpwi   0,r5,0
        beq     1f
  
 +#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
        /* find out where we are now */
        bcl     20,31,$+4
  0:    mflr    r8                      /* r8 = runtime addr here */
        addis   r8,r8,(_stext - 0b)@ha
        addi    r8,r8,(_stext - 0b)@l   /* current runtime base addr */
        bl      prom_init
 +#endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
 +
 +      /* We never return. We also hit that trap if trying to boot
 +       * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
        trap
 -#endif
  
  /*
   * Check for BootX signature when supporting PowerMac and branch to
@@@ -514,8 -511,11 +514,11 @@@ InstructionTLBMiss
        and     r1,r1,r2                /* writable if _RW and _DIRTY */
        rlwimi  r3,r3,32-1,30,30        /* _PAGE_USER -> PP msb */
        rlwimi  r3,r3,32-1,31,31        /* _PAGE_USER -> PP lsb */
-       ori     r1,r1,0xe14             /* clear out reserved bits and M */
+       ori     r1,r1,0xe04             /* clear out reserved bits */
        andc    r1,r3,r1                /* PP = user? (rw&dirty? 2: 3): 0 */
+ BEGIN_FTR_SECTION
+       rlwinm  r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
+ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
        mtspr   SPRN_RPA,r1
        mfspr   r3,SPRN_IMISS
        tlbli   r3
@@@ -588,8 -588,11 +591,11 @@@ DataLoadTLBMiss
        and     r1,r1,r2                /* writable if _RW and _DIRTY */
        rlwimi  r3,r3,32-1,30,30        /* _PAGE_USER -> PP msb */
        rlwimi  r3,r3,32-1,31,31        /* _PAGE_USER -> PP lsb */
-       ori     r1,r1,0xe14             /* clear out reserved bits and M */
+       ori     r1,r1,0xe04             /* clear out reserved bits */
        andc    r1,r3,r1                /* PP = user? (rw&dirty? 2: 3): 0 */
+ BEGIN_FTR_SECTION
+       rlwinm  r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
+ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
        mtspr   SPRN_RPA,r1
        mfspr   r3,SPRN_DMISS
        tlbld   r3
@@@ -656,8 -659,11 +662,11 @@@ DataStoreTLBMiss
        stw     r3,0(r2)                /* update PTE (accessed/dirty bits) */
        /* Convert linux-style PTE to low word of PPC-style PTE */
        rlwimi  r3,r3,32-1,30,30        /* _PAGE_USER -> PP msb */
-       li      r1,0xe15                /* clear out reserved bits and M */
+       li      r1,0xe05                /* clear out reserved bits & PP lsb */
        andc    r1,r3,r1                /* PP = user? 2: 0 */
+ BEGIN_FTR_SECTION
+       rlwinm  r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
+ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
        mtspr   SPRN_RPA,r1
        mfspr   r3,SPRN_DMISS
        tlbld   r3
index 204ae5c402fad507d1b333f18fb70befecc87700,740ef56a1550c75af26e8cf551655e03906aa08e..dfe316b161a9a16c658632da5002135e5443af97
@@@ -1,6 -1,6 +1,6 @@@
  config PPC_PS3
        bool "Sony PS3"
 -      depends on PPC_MULTIPLATFORM && PPC64
 +      depends on PPC64 && PPC_BOOK3S
        select PPC_CELL
        select USB_ARCH_HAS_OHCI
        select USB_OHCI_LITTLE_ENDIAN
@@@ -128,6 -128,13 +128,13 @@@ config PS3_FLAS
          be disabled on the kernel command line using "ps3flash=off", to
          not allocate this fixed buffer.
  
+ config PS3_VRAM
+       tristate "PS3 Video RAM Storage Driver"
+       depends on FB_PS3=y && BLOCK && m
+       help
+         This driver allows you to use excess PS3 video RAM as volatile
+         storage or system swap.
  config PS3_LPM
        tristate "PS3 Logical Performance Monitor support"
        depends on PPC_PS3
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