clk: tegra: Initialize PLL_C to sane rate on Tegra30

If the bootloader does not touch PLL_C it will stay in its reset state,
failing to lock when enabled. This leads to consumers of this clock to
fail probing. Fix this by always programming the PLL with a sane rate,
which allows it to lock, at startup.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 0478565cf292a1594af351df8ee93daeae72d33a..236e2db9a716bb97066f414e37538edbacf8dc4b 100644 (file)
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1372,6 +1372,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
        { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
        { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
        { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
+       { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
        { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
        { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
        { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },