clk: samsung: exynos4: export sclk_hdmiphy clock

Export sclk_hdmiphy clock to be usable from DT.

Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 7e2adcbee4cd9fbc8afb6436f2e39e81ad7d9f0b..c4df294bb7fb16090a2169f7fb32bdcc48036c06 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -428,7 +428,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
 /* fixed rate clocks generated inside the soc */
 static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
        FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
-       FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+       FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
        FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
 };
 

diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 3ff13bcbe56c2a369a19d8eba4976a19b3892dc5..1106ca540a9629fa73fcfcc0290f376936691dcd 100644 (file)
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -33,6 +33,7 @@
 #define CLK_MOUT_MPLL_USER_C   18 /* Exynos4x12 only */
 #define CLK_MOUT_CORE          19
 #define CLK_MOUT_APLL          20
+#define CLK_SCLK_HDMIPHY       22
 
 /* gate for special clocks (sclk) */
 #define CLK_SCLK_FIMC0         128