m68knommu: move the 520x platform code into the common ColdFire code directory

All these separate directories for each ColdFire CPU SoC varient seems like
overkill. The majority of them only contain a single small config file. Move
these into the common ColdFire code directory.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 8303f3b136863ae601b07e44f1cd326b06a34c25..090707af5a177528b5a6feb656af35e9fe96da30 100644 (file)
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -115,7 +115,6 @@ core-$(CONFIG_M68000)               += arch/m68k/platform/68328/
 core-$(CONFIG_M68EZ328)                += arch/m68k/platform/68EZ328/
 core-$(CONFIG_M68VZ328)                += arch/m68k/platform/68VZ328/
 core-$(CONFIG_COLDFIRE)                += arch/m68k/platform/coldfire/
-core-$(CONFIG_M520x)           += arch/m68k/platform/520x/
 core-$(CONFIG_M523x)           += arch/m68k/platform/523x/
 core-$(CONFIG_M5249)           += arch/m68k/platform/5249/
 core-$(CONFIG_M527x)           += arch/m68k/platform/527x/

diff --git a/arch/m68k/platform/520x/Makefile b/arch/m68k/platform/520x/Makefile
deleted file mode 100644 (file)
index 03e29d1..0000000
--- a/arch/m68k/platform/520x/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Makefile for the M5208 specific file.
-#
-
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs.  You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-
-obj-y := config.o

diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c
deleted file mode 100644 (file)
index 3264b88..0000000
--- a/arch/m68k/platform/520x/config.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/***************************************************************************/
-
-/*
- *  linux/arch/m68knommu/platform/520x/config.c
- *
- *  Copyright (C) 2005,      Freescale (www.freescale.com)
- *  Copyright (C) 2005,      Intec Automation (mike@steroidmicros.com)
- *  Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
- *  Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
- */
-
-/***************************************************************************/
-
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <asm/machdep.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfuart.h>
-#include <asm/mcfgpio.h>
-
-/***************************************************************************/
-
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-       MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
-       MCFGPF(CS, 9, 3),
-       MCFGPF(FECI2C, 16, 4),
-       MCFGPF(QSPI, 24, 4),
-       MCFGPF(TIMER, 32, 4),
-       MCFGPF(UART, 40, 8),
-       MCFGPF(FECH, 48, 8),
-       MCFGPF(FECL, 56, 8),
-};
-
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
-
-/***************************************************************************/
-
-#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
-
-static void __init m520x_qspi_init(void)
-{
-       u16 par;
-       /* setup Port QS for QSPI with gpio CS control */
-       writeb(0x3f, MCF_GPIO_PAR_QSPI);
-       /* make U1CTS and U2RTS gpio for cs_control */
-       par = readw(MCF_GPIO_PAR_UART);
-       par &= 0x00ff;
-       writew(par, MCF_GPIO_PAR_UART);
-}
-
-#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
-
-/***************************************************************************/
-
-static void __init m520x_uarts_init(void)
-{
-       u16 par;
-       u8 par2;
-
-       /* UART0 and UART1 GPIO pin setup */
-       par = readw(MCF_GPIO_PAR_UART);
-       par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
-       par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
-       writew(par, MCF_GPIO_PAR_UART);
-
-       /* UART1 GPIO pin setup */
-       par2 = readb(MCF_GPIO_PAR_FECI2C);
-       par2 &= ~0x0F;
-       par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
-               MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
-       writeb(par2, MCF_GPIO_PAR_FECI2C);
-}
-
-/***************************************************************************/
-
-static void __init m520x_fec_init(void)
-{
-       u8 v;
-
-       /* Set multi-function pins to ethernet mode */
-       v = readb(MCF_GPIO_PAR_FEC);
-       writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
-
-       v = readb(MCF_GPIO_PAR_FECI2C);
-       writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
-}
-
-/***************************************************************************/
-
-void __init config_BSP(char *commandp, int size)
-{
-       mach_sched_init = hw_timer_init;
-       m520x_uarts_init();
-       m520x_fec_init();
-#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
-       m520x_qspi_init();
-#endif
-}
-
-/***************************************************************************/

diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index ef729b173eb8acace09d6916eaaf4e91522ec56a..60c1efade41ecb477fcede6ccf58839ded0419d3 100644 (file)
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -17,7 +17,7 @@ asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
 obj-$(CONFIG_COLDFIRE) += cache.o clk.o device.o dma.o entry.o vectors.o
 obj-$(CONFIG_M5206)    += m5206.o timers.o intc.o reset.o
 obj-$(CONFIG_M5206e)   += m5206.o timers.o intc.o reset.o
-obj-$(CONFIG_M520x)    += pit.o intc-simr.o reset.o
+obj-$(CONFIG_M520x)    += m520x.o pit.o intc-simr.o reset.o
 obj-$(CONFIG_M523x)    += pit.o dma_timer.o intc-2.o reset.o
 obj-$(CONFIG_M5249)    += timers.o intc.o reset.o
 obj-$(CONFIG_M527x)    += pit.o intc-2.o reset.o

diff --git a/arch/m68k/platform/coldfire/m520x.c b/arch/m68k/platform/coldfire/m520x.c
new file mode 100644 (file)
index 0000000..3264b88
--- /dev/null
+++ b/arch/m68k/platform/coldfire/m520x.c
@@ -0,0 +1,103 @@
+/***************************************************************************/
+
+/*
+ *  linux/arch/m68knommu/platform/520x/config.c
+ *
+ *  Copyright (C) 2005,      Freescale (www.freescale.com)
+ *  Copyright (C) 2005,      Intec Automation (mike@steroidmicros.com)
+ *  Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
+ *  Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfgpio.h>
+
+/***************************************************************************/
+
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+       MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
+       MCFGPF(CS, 9, 3),
+       MCFGPF(FECI2C, 16, 4),
+       MCFGPF(QSPI, 24, 4),
+       MCFGPF(TIMER, 32, 4),
+       MCFGPF(UART, 40, 8),
+       MCFGPF(FECH, 48, 8),
+       MCFGPF(FECL, 56, 8),
+};
+
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+
+/***************************************************************************/
+
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
+
+static void __init m520x_qspi_init(void)
+{
+       u16 par;
+       /* setup Port QS for QSPI with gpio CS control */
+       writeb(0x3f, MCF_GPIO_PAR_QSPI);
+       /* make U1CTS and U2RTS gpio for cs_control */
+       par = readw(MCF_GPIO_PAR_UART);
+       par &= 0x00ff;
+       writew(par, MCF_GPIO_PAR_UART);
+}
+
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
+
+/***************************************************************************/
+
+static void __init m520x_uarts_init(void)
+{
+       u16 par;
+       u8 par2;
+
+       /* UART0 and UART1 GPIO pin setup */
+       par = readw(MCF_GPIO_PAR_UART);
+       par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
+       par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
+       writew(par, MCF_GPIO_PAR_UART);
+
+       /* UART1 GPIO pin setup */
+       par2 = readb(MCF_GPIO_PAR_FECI2C);
+       par2 &= ~0x0F;
+       par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
+               MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
+       writeb(par2, MCF_GPIO_PAR_FECI2C);
+}
+
+/***************************************************************************/
+
+static void __init m520x_fec_init(void)
+{
+       u8 v;
+
+       /* Set multi-function pins to ethernet mode */
+       v = readb(MCF_GPIO_PAR_FEC);
+       writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
+
+       v = readb(MCF_GPIO_PAR_FECI2C);
+       writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+       mach_sched_init = hw_timer_init;
+       m520x_uarts_init();
+       m520x_fec_init();
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
+       m520x_qspi_init();
+#endif
+}
+
+/***************************************************************************/